PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 181

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
The following figure gives an example of an interrupt controlled reception sequence,
supposed that a long frame (132 bytes) followed by two short frames (12 bytes each) are
received.
Figure 85
DMA Mode
If the RFIFOB contains 64 bytes, the IPAC autonomously requests a block data transfer
by DMA activating the DRQRA/B line as long as the start of the 64th read cycle. This
forces the DMA controller to continuously perform bus cycles till 64 bytes are transferred
from the IPAC to the system memory.
If the RFIFOB contains less than 64 bytes (one short frame or the last part of a long
frame) the IPAC requests a block data transfer depending on the contents of the RFIFOB
according to the following table:
Serial
Interface
IPAC
CPU
Interface
Receive Frame 1
64
RPF
64 Bytes
Interrupt Driven Reception Sequence Example
RD
...
64
RMC
(132 Bytes)
RPF
4
64 Bytes
RD
...
12
RMC
12
RME
181
...
RMC
RME
Operational Description
...
RMC
RME
PSB 2115
PSF 2115
...
ITD09652
RMC
11.97