PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 142

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

withdrawn. After a successful bus access, the IPAC is automatically set into a lower
priority class, that is, a new bus access cannot be performed until the status "bus free"
is indicated in two successive frames.
If none of the devices connected to the IOM interface request access to the D and C/I
channels, the TIC bus address 7 will be present. The device with this address will
therefore have access, by default, to the D and C/I channels.
Note: Bit BAC (CIX0 register) should be reset by the P when access to the C/I channels
The availability of the S/T interface D channel is indicated in bit 5 "Stop/Go" (S/G) of the
DD last octet of Ch2 channel (figure 68).
S/G = 1 : stop
S/G = 0 : go
Figure 68
The Stop/Go bit is available to other layer-2 devices connected to the IOM to determine
if they can access the S/T bus D channel.
The A/B bit is used by the exchange (controlled by layer 1) to temporarily prohibit D-
channel transmission (A/B = ’0’) when only a single D-channel controller on the linecard
handles more lines (ELIC concept). For most applications D-channel transmission is
usually permitted (A/B = ’1’).
Semiconductor Group
is no more requested, to grant other devices access to the D and C/I channels.
B1
Structure of Last Octet of Ch2 on DD
B2
MON0
D
CI0
MR
MX
IC1
Stop/Go
IC2
142
MON1
S/G A/B
Available/Blocked
CI1
MR
MX
Functional Description
S/G
ITD09693
A/B
PSB 2115
PSF 2115
11.97