PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 273

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
4.4.6
Value after reset: FC
AOE
OE7 - OE2 ... Output Enable for AUX7-2
0: Pin AUX7-2 is configured as output. The value of the corresponding bit in the ATX
register is driven on AUX7-2.
1: Pin AUX7-2 is configured as input. The value of the corresponding bit can be read from
the ARX register.
Note: If pins AUX7, AUX6 are to be used as interrupt input, OE7,OE6 must be set to 1.
4.4.7
Value after reset: (not defined)
ARX
AR7-AR2 ... Auxiliary Receive
The value of AR7-AR2 reflects the level at pin AUX7-AUX2 at that time when ARX is read
by the host. If the mask bit for AUX7,6 is set in the MASK register, no interrupt is
generated to the IPAC, however, the current state at pin AUX7,6 can be read from
AR7,6.
Note: Pin AUX2 is only available in TE mode and not in LT modes.
Pin AUX2 is only available in TE mode and not in LT modes.
In LT modes the pins AUX 3-5 are only available if the PCM interface is disabled
(PCFG:PLD=1).
The general purpose I/O pins are input after reset (OEx=1).
In LT modes the pins AUX 3-5 are only available if the PCM interface is disabled
(PCFG:PLD=1).
AOE - Auxiliary Output Enable (Read/Write)
7
ARX - Auxiliary Interface Receive Register (Read)
7
OE7
AR7
OE6
AR6
H
OE5
AR5
OE4
AR4
273
OE3
AR3
OE2
AR2
Detailed Register Description
0
0
0
0
0
0
PSB 2115
PSF 2115
11.97
(C4)
(C5)