PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 155

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
3
3.1
After a reset the IPAC is in an idle state and its registers are loaded with specific values.
B-Channel registers
The B-Channel related registers are located in the address range 00h - 73h. Their reset
values are described in table 17.
Table 17 RESET Values for B-Channel Registers
Register
CCR1
CCR2
MODEB
STARB
ISTAB
MASKB
EXIRB
CMDRB
XBCH
RBCHB
XCCR
RCCR
Operational Description
RESET
Value after
Reset (hex)
00
00
00
48
00
00
00
00
Meaning
– Power down mode
– Serial port configuration: NRZ coding
– Interframe time fill: idle (’1’) are output on DU
– Transmit data enabled
– Receive frame start interrupt enable: RFS disabled
– Mode select: reserved mode
– Address mode: 1 byte address field
– Receivers inactive
– Continuous frame transmission: delayed XPR
interrupt
– Receiver active: HDLC receiver inactive
– Test loop disabled
– XFIFO write enable
– Receive line inactive
– No commands executing
– Transmitter inactive
– No interrupt pending
– All interrupts enabled
– No commands
– Interrupt controlled data transfer
– Transmit continuously disabled
– 1-bit time-slot
– Special output control: TX on DU, RX on DD
155
Operational Description
PSB 2115
PSF 2115
11.97