PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 297

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
Figure 117
Description of the receive PLL (RPLL) of the IPAC
The receive PLL performs phase tracking each 250 s after detecting the phase
between the F/L transition of the receive signal and the recovered clock. Phase
adjustment is done by adding or subtracting 65 ns to or from a 1.536-MHz clock cycle.
The 1.536-MHz clock is than used to generate any other clock synchronized to the line.
During (re)synchronization an internal reset condition may effect the 1.536-MHz clock to
have high or low times as short as 130 ns. After the S/T interface frame has achieved
the synchronized state (after three consecutive valid pairs of code violations) the FSC
output in TE mode is set to a specific phase relationship, thus causing once an irregular
FSC timing.
Lead
Up/Down
7.68 MHz
Counter
Divider
÷ 5 ± 1
Block Diagram of XPLL
Lag
Down
Up
1.536 MHz
FSC 8 kHz
Detector
Phase
297
8 kHz
Divider
Divider
÷ 192
÷ 8
Electrical Characteristics
192 kHz
ITS09665
PSB 2115
PSF 2115
11.97