PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 243

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
Note: SAP1, SAP2: two programmable address values for the first received address
TMD ...Timer Mode
Sets the operating mode of the IPAC timer 1. In the external mode (0) the timer is
controlled by the processor. It is started by setting the STI bit in CMDRD and it is stopped
by a write of the TIMR1 register. In the internal mode (1) the timer is used internally by
the IPAC for timeout and retry conditions (handling of LAPD/HDLC protocol in auto
mode).
RAC ... Receiver Active
The HDLC receiver is activated when this bit is set to “1”.
DIM2-0 ... Digital Interface Modes
These bits define the characteristics of the IOM Data Ports (DU, DD) according to
following table:
Table 27 IOM
Characteristics
DIM2, DIM1, DIM0
Last octet of IOM channel 2
used for TIC bus access
Stop/go bit evaluated for
D-channel access handling
Reserved
Applications
TE mode
LT-T mode
with D-channel collision resolution
LT-T, LT-S modes
with transparent D-channel
byte (in the case of an address field longer than 1 byte);
SAPG = fixed value FC / FE
TEI1, TEI2: two programmable address values for the second (or the only, in the
case of a one-byte address) received address byte; TEIG = fixed value FF
®
-2 Modes
H
.
000
243
x
001
x
x
x
Detailed Register Description
010
x
011
x
x
x
PSB 2115
PSF 2115
100...111
H
x
11.97