PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 219

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
received frame. The valid byte count must therefore be determined by reading the
registers RBCHB, RBCLB following the RME interrupt.
The corresponding DRQRA/B pin remains ’high’ as long as the RFIFOB requires data
transfers. It is deactivated upon the rising edge of the 63rd DMA transfer or, if n < 64 or
n is the remainder of a long frame, upon the falling edge of the last DMA transfer.
If n
line will go high again as soon as CS goes high, thus indicating further bytes to fetch.
4.2.2
XFIFOB
Interrupt Controlled Data Transfer (Interrupt Mode, selected by XBCH:DMA=0):
Up to 64 bytes of transmit data can be written to the XFIFOB following an XPR interrupt.
DMA Controlled Data Transfer (DMA Mode, selected by XBCH:DMA=1):
Prior to any data transfer, the actual byte count of the frame to be transmitted must be
written to the XBCH, XBCL registers by the user.
If data transfer is then initiated via the CMDRB register (command XTF or XIF), the IPAC
autonomously requests the correct amount of block data transfers (n
n = 0, 1, …).
The corresponding DRQTA/B pin remains ’high’ as long as the XFIFOB requires data
transfers. It is deactivated upon the rising edge of WR in the DMA transfer 63 or n-1
respectively. The DMA controller must take care to perform the last DMA transfer. If it is
missing, the DRQTA/B line will go active again when CS is raised.
Although the address range covers only 32 byte (similar to HSCX-TE) the FIFO depth is
64 byte as the read address does not need to be reprogrammed. Addresses within the
address space of the FIFO’s are interpreted equally, i.e. the actual data byte can be
accessed with any address within the valid scope.
64 and the DMA controller does not perform the 64th DMA cycle, the DRQRA/B
7
XFIFOB - Transmit FIFO B-Channel (WRITE))
1 byte:
n bytes:
Transmit data
219
XBCL = 0
XBCL = n - 1
Detailed Register Description
0
64 + remainder,
(00-1F/40-5F)
PSB 2115
PSF 2115
11.97