PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 263

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
4.3.33
Value after reset: 00
STCR
TSF ... Terminal Specific Functions (only in TE mode)
0
1
Note: The TSF-bit will be cleared only by a hardware reset.
TBA2-0 ... TIC Bus Address
Defines the individual address for the IPAC on the IOM-bus.
This address is used to access the C/I- and D-channel on the IOM.
Note: One device liable to transmit in C/I- and D-fields on the IOM should always be
ST1 ... Synchronous Transfer 1
When set, causes the IPAC to generate a SIN-interrupt status (ISTAD-register) at the
beginning of an IOM-frame.
ST0 ... Synchronous Transfer 0
When set, causes the IPAC to generate a SIN-interrupt status (ISTAD-register) at the
middle of an IOM-frame.
No terminal specific functions
The terminal specific functions are activated, such as
– Watchdog Timer
– Subscriber/Exchange Awake (EAW).
In this case the EAW-line is always an input signal which can serve as a request
signal from the subscriber to initiate the awake function in a terminal.
A falling edge on the EAW-line generates an SAW-interrupt (EXIRD). When the
RSS-bit in the CIX0-register is zero, a falling edge on the EAW-line (Subscriber
Awake) or a C/I-code change (Exchange Awake) initiates a reset pulse.
When the RSS-bit is set to one a reset pulse is triggered only by the expiration of
the watchdog timer (see also CIX0-register description).
The ’Exchange Awake’ functionality is only available in TE mode.
given the address value “7”.
STCR - Synchronous Transfer Control Register (Write)
7
TSF
TBA2 TBA1 TBA0
H
263
ST1
ST0
Detailed Register Description
SC1
0
SC0
PSB 2115
PSF 2115
11.97
(B7)