PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 234

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

CCR1
TSAX
number of bits per time-slot can be programmed via XCCR.
XCS2, XCS1 … Transmit Clock Shift, Bit 2-1
Together with the XCS0 in CCR2, the transmit clock shift can be adjusted.
4.2.21
Value after reset: 02
PU … Switches between Power Up and Power Down mode
0 … power down (standby)
1 … power up (active)
Note: In order to switch the IPAC in power down mode it is necessary to program ITF=0
SC ... Serial Port Configuration
0 … NRZ data encoding
1 … NRZI data encoding
ITF … Interframe Time Fill
ITF determines the idle state (= no data to send) of the transmit data pin (DU)
0 … Continuous IDLE sequences are output (DU pin remains in the ‘1’ state)
1 … Continuous FLAG sequences are output (‘01111110’ bit patterns)
Note: ITF must be set to ’0’ for power down mode.
4.2.22
Value after reset: (not defined)
TSNX … Time-Slot Number Transmit
Selects one of up 64 possible time-slots (00
Semiconductor Group
together with PU=0.
CCR1 - Channel Configuration Register 1 (READ/WRITE)
7
TSAX - Time-Slot Assignment Register Transmit (WRITE)
7
PU
H
SC
0
TSNX
0
234
ITF
H
– 3F
H
) in which data is transmitted. The
0
Detailed Register Description
2
XCS2 XCS1
1
1
0
0
0
PSB 2115
PSF 2115
(2F/6F)
(30/70)
11.97