PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 20

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
Pin No. Symbol Input (I)
29
30
Auxiliary Interface
31
DACKA
DACKB
AUX0
Output (O)
I
I/O
Function
DMA Acknowledge (channel A/B)
When LOW, this input signal from the DMA controller
indicates to the IPAC, that the requested DMA cycle
controlled via DRQTA/B and DRQRA/B is in progress,
i.e. the DMA controller has achieved bus mastership
from the CPU and will start data transfer cycles (either
read or write).
Together with RD, if DMA has been requested from the
receiver, or with WR, if DMA has been requested from
the transmitter, this input works like CS to enable a
data byte to be read from or written to the top of the
receive or transmit FIFO of the specified channel.
If DACKA/B is active, the input on pins A0-7 is ignored
and the FIFO’s are implicitly selected.
If the DACKA/B signals are not used, these pins must
be connected to VDD.
Auxiliary Port 0
TE-Mode: DRQTA (output)
DMA Request Transmitter (channel A)
The transmitter of the IPAC requests DMA data
transfer by activating this line.
The DRQTA remains HIGH as long as the transmit
FIFO requires data transfer.
The amount of data bytes to be transferred from
system memory to the IPAC (= byte count) must be
written first to the XBCH, XBCL register.
Always blocks of data (n x 64 bytes + REST, n=0, 1, ..)
are transferred till the byte count is reached.
DRQTA is deactivated immediately following the falling
edge of the last WR cycle.
LT-T/LT-S Mode: CH0 (input)
IOM-2 Channel Select 0
Together with CH1 (pin AUX1) and CH2 (pin AUX2),
this pin selects one of eight channels on the IOM-2
interface.
20
PSB 2115
PSF 2115
Overview
11.97