PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 231

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
4.2.17
Value after reset: 00
CCR2
SOC … Special Output Control
0 … B-Channel data is transmitted on DU, received on DD pin (normal case)
1 … B-Channel data is transmitted on DD, received on DU pin
XCS0, RCS0 … Transmit/Receive Clock Shift, Bit 0
Together with bits XCS2, XCS1 (RCS2, RCS1) in TSAX (TSAR) the clock shift relative
to the frame synchronization signal of the transmit (receive) time-slot can be adjusted.
A clock shift of 0 … 7 bits is programmable.
TXD … Transmitter Disable
0 ... DU pin is enabled during the programmed timeslot
1 ... DU pin is disabled (high impedant) during the programmed timeslot
Note: This mode can be used to deactivate the B-channel timeslot in push-pull
RIE … Receive Frame Start Interrupt Enable
When RIE is set, the RFS interrupt (via EXIRB) is enabled.
DIV … Data Inversion
If enabled (DIV=1), data is transmitted and received inverted. This feature is described
in detail in chapter 2.1.12.
Note: This option is only valid if NRZ data encoding is selected (CCR1:SC=0).
configuration.
CCR2 - Channel Configuration Register 2 (READ/WRITE)
7
SOC
H
0
XCS0 RCS0
231
TXD
0
Detailed Register Description
RIE
0
DIV
PSB 2115
PSF 2115
(2C/6C)
11.97