AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 126

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

126
63:10
Bit
9
8
7
6
5
4
3
2
1
0
Name
RSVD
DMI_TF
DMI_STALL
DMM_SUSP
DMI_TSS
DMM_CACHE
DMI_ICEBP
DMI_DBG
DMI_EXT
DMI_GPF
DMI_INST
31505E
Description
Reserved. Write as read.
DMI Trap Flag.
0: Disable DMI single stepping.
1: If DMI_STALL (bit 8) is 0, DMI occurs after the successful execution of each instruc-
DMI Stall.
0: If not in DMM, DMI conditions cause DMIs.
1: DMI conditions cause a debug stall.
Enable SUSP# during DMM. Enable SUSP# during DMM mode.
0: Disable.
1: Enable.
Task Switch Debug Fault Control.
0: Task switch debug faults cause debug exceptions.
1: Task switch debug exceptions cause DMIs when not in DMM.
Cache Control during DMM.
0: Don’t change CR0 CD and NW bits when entering DMM.
1: Set CR0, CD and NW bits when entering DMM
Enable DMIs on ICEBP (F1) Instructions.
0: Disable.
1: Enable.
Enable Replacing Debug Exceptions as DMIs.
0: Disable.
1: Enable.
Enable External TDBGI Pin. Enable DMIs caused by the TDBGI pin (BGD368 ball C11;
BGU396 ball T25) when not in DMM.
0: Disable.
1: Enable.
Enable General Protection Fault Conditions causing DMIs. When enabled and not in
DMM mode, allow general protection faults to generate DMIs.
0: Disable.
1: Enable.
Enable DMI Instructions. Enable DMI instructions DMINT and RDM. If not enabled,
executing a DMI instruction generates an invalid operation fault.
0: Disable.
1: Enable.
tion. If DMI_STALL is 1, debug stall occurs after the successful execution of each
instruction.
DMI Control Register Bit Descriptions
.
AMD Geode™ GX Processors Data Book
CPU Core Register Descriptions