AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 518
AGXD533AAXF0CC
Manufacturer Part Number
AGXD533AAXF0CC
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.AGXD533AAXF0CC.pdf
(539 pages)
Specifications of AGXD533AAXF0CC
Device Core
X86
Device Core Size
64b
Frequency (max)
400MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5V
Operating Supply Voltage (max)
1.58V
Operating Supply Voltage (min)
1.42V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
368
Package Type
BGD
Lead Free Status / Rohs Status
Not Compliant
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PSLLD Packed Shift Left Logical Dword
PSLLQ Packed Shift Left Logical Qword
PSLLW Packed Shift Left Logical Word
PSRAD Packed Shift Right Arithmetic Dword
PSRAW Packed Shift Right Arithmetic Word
PSRLD Packed Shift Right Logical Dword
PSRLQ Packed Shift Right Logical Qword
PSRLW Packed Shift Right Logical Word
PSUBB Subtract Byte With Wrap-Around
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by immediate
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by immediate
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by immediate
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by immediate
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by immediate
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by immediate
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by immediate
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by immediate
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX
®
Instructions
31505E
Table 8-28. MMX
0FF2 [11 mm1
mm2]
0FF2 [mod mm r/m]
0F72 [11 110 mm] #
0FF3 [11 mm1
mm2]
0FF3 [mod mm r/m]
0F73 [11 110 mm] #
0FF1 [11 mm1
mm2]
0FF1 [mod mm r/m]
0F71 [11 110mm] #
0FE2 [11 mm1
mm2]
0FE2 [mod mm r/m]
0F72 [11 100 mm] #
0FE1 [11 mm1
mm2]
0FE1 [mod mm r/m]
0F71 [11 100 mm] #
0FD2 [11 mm1
mm2]
0FD2 [mod mm r/m]
0F72 [11 010 mm] #
0FD3 [11 mm1
mm2]
0FD3 [mod mm r/m]
0F73 [11 010 mm] #
0FD1 [11 mm1
mm2]
0FD1 [mod mm r/m]
0F71 [11 010 mm] #
0FF8 [11 mm1
mm2]
0FF8 [mod mm r/m]
Opcode
®
MMX reg 1 [dword] <--- MMX reg 1 [dword] shift left by MMX
reg 2 [dword], shifting in zeroes
MMX reg [dword] <--- MMX reg [dword] shift left by
memory [dword], shifting in zeroes
MMX reg [dword] <--- MMX reg [dword] shift left by [im byte],
shifting in zeroes
MMX reg 1 [qword] <--- MMX reg 1 [qword] shift left by MMX
reg 2 [qword], shifting in zeroes
MMX reg [qword] <--- MMX reg [qword] shift left by memory
[qword], shifting in zeroes
MMX reg [qword] <--- MMX reg [qword]shift left by [im byte],
shifting in zeroes
MMX reg 1 [word] <--- MMX reg 1 [word] shift left by MMX reg
2 [word], shifting in zeroes
MMX reg [word] <--- MMX reg [word] shift left by memory
[word], shifting in zeroes
MMX reg [word] <--- MMX reg [word] shift left by [im byte],
shifting in zeroes
MMX reg 1 [dword] <--- MMX reg 1 [dword] shift right by MMX
reg 2 [dword], shifting in sign bits
MMX reg [dword] <--- MMX reg [dword] shift right by memory
[dword], shifting in sign bits
MMX reg [dword] <--- MMX reg [dword] shift right by [im byte],
shifting in sign bits
MMX reg 1 [word] <--- MMX reg 1 [word] shift right by MMX
reg 2 [word], shifting in sign bits
MMX reg [word] <--- MMX reg [word] shift right by memory
[word], shifting in sign bits
MMX reg [word] <--- MMX reg [word] shift right by [im byte],
shifting in sign bits
MMX reg 1 [dword] <--- MMX reg 1 [dword] shift right by MMX
reg 2 [dword], shifting in zeroes
MMX reg [dword] <--- MMX reg [dword] shift right by mem-
ory[dword], shifting in zeroes
MMX reg [dword] <--- MMX reg [dword]shift right by [im byte],
shifting in zeroes
MMX reg 1 [qword] <--- MMX reg 1 [qword] shift right by MMX
reg 2 [qword], shifting in zeroes
MMX reg [qword] <--- MMX reg [qword] shift right by memory
[qword], shifting in zeroes
MMX reg [qword] <--- MMX reg [qword] shift right by [im byte],
shifting in zeroes
MMX reg 1 [word] <--- MMX reg 1 [word] shift right by MMX
reg 2 [word], shifting in zeroes
MMX reg [word] <--- MMX reg [word] shift right by memory
[word], shifting in zeroes
MMX reg [word] <--- MMX reg [word] shift right by imm [word],
shifting in zeroes
MMX reg 1 [byte] <--- MMX reg 1 [byte] - MMX reg 2 [byte]
MMX reg [byte] <--- MMX reg [byte] - memory [byte]
Instruction Set (Continued)
Operation
AMD Geode™ GX Processors Data Book
Clock Ct
Instruction Set
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
2
2
2
2
2
Notes
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