AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 514

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

514
EMMS Empty MMX State
MASKMOVQ Streaming (Cache Bypass) Store Using Byte Mask (Using EDI Register)
MOVD Move Doubleword
MOVNTQ Streaming (Cache Bypass) Store
MOVQ Move Quardword
PACKSSDW Pack Dword with Signed Saturation
PACKSSWB Pack Word with Signed Saturation
PACKUSWB Pack Word with Unsigned Saturation
PADDB Packed Add Byte with Wrap-Around
PADDD Packed Add Dword with Wrap-Around
PADDSB Packed Add Signed Byte with Saturation
PADDSW Packed Add Signed Word with Saturation
PADDUSB Add Unsigned Byte with Saturation
MMX Register1with MMX Register2
Register to MMX Register
MMX Register to Register
Memory to MMX Register
MMX Register to Memory
MMX Register to Memory64
MMX Register 2 to MMX Register 1
MMX Register 1 to MMX Register 2
Memory to MMX Register
MMX Register to Memory
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to Register
MMX Register 2 to MMX Register 1
Memory to Register
MMX Register 2 to MMX Register 1
Memory to Register
MMX
®
Instructions
31505E
0F77
0FF7 [11 mm1
mm2]
0F6E [11 mm reg]
0F7E [11 mm reg]
0F6E [mod mm r/m]
0F7E [mod mm r/m]
0FE7 [mod mm r/m]
0F6F [11 mm1
mm2]
0F7F [11 mm1
mm2]
0F6F [mod mm r/m]
0F7F [mod mm r/m]
0F6B [11 mm1
mm2]
0F6B [mod mm r/m]
0F63 [11 mm1 mm2]
0F63 [mod mm r/m]
0F67 [11 mm1 mm2]
0F67 [mod mm r/m]
0FFC [11 mm1
mm2]
0FFC [mod mm r/m]
0FFE [11 mm1
mm2]
0FFE [mod mm r/m]
0FEC [11 mm1
mm2]
0FEC [mod mm r/m]
0FED [11 mm1
mm2]
0FED [mod mm r/m]
0FDC [11 mm1
mm2]
0FDC [mod mm r/m]
Opcode
Table 8-28. MMX
Tag Word <--- FFFFh (empties the floating point tag word)
memory [edi] [byte] <--- MMX reg 2 [Sign byte] ? MMX reg 1
[byte] : memory [edi] [byte]
MMX reg [qword] <--- zero extend --- reg [dword]
reg [qword] <--- MMX reg [low dword]
MMX regr [qword] <--- zero extend --- memory [dword]
Memory [dword] <--- MMX reg [low dword]
Memory64 [qword] <--- MMX reg [qword]
MMX reg 1 [qword] <--- MMX reg 2 [qword]
MMX reg 2 [qword] <--- MMX reg 1 [qword]
MMX reg [qword] <--- memory[qword]
Memory [qword] <--- MMX reg [qword]
MMX reg 1 [qword] <--- packdw, signed sat --- MMX reg 2,
MMX reg 1
MMX reg [qword] <--- packdw, signed sat --- memory, MMX
reg
MMX reg 1 [qword] <--- packwb, signed sat --- MMX reg 2,
MMX reg 1
MMX reg [qword] <--- packwb, signed sat --- memory, MMX
reg
MMX reg 1 [qword] <--- packwb, unsigned sat --- MMX reg 2,
MMX reg 1
MMX reg [qword] <--- packwb, unsigned sat --- memory, MMX
reg
MMX reg 1 [byte] <--- MMX reg 1 [byte] + MMX reg 2 [byte]
MMX reg[byte] <--- memory [byte] + MMX reg [byte]
MMX reg 1 [sign dword] <--- MMX reg 1 [sign dword] + MMX
reg 2 [sign dword]
MMX reg [sign dword] <--- memory [sign dword] + MMX reg
[sign dword]
MMX reg 1 [sign byte] <--- sat --- (MMX reg 1 [sign byte] +
MMX reg 2 [sign byte])
MMX reg [sign byte] <--- sat --- (memory [sign byte] + MMX
reg [sign byte])
MMX reg 1 [sign word] <--- sat --- (MMX reg 1 [sign word] +
MMX reg 2 [sign word])
MMX reg [sign word] <--- sat --- (memory [sign word] + MMX
reg [sign word])
MMX reg 1 [byte] <--- sat --- (MMX reg 1 [byte] + MMX reg 2
[byte])
MMX reg [byte] <--- sat --- (memory [byte] + MMX reg [byte])
®
Instruction Set
Operation
AMD Geode™ GX Processors Data Book
Clock Ct
Instruction Set
1
2
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Notes
1