AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 151

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

CPU Core Register Descriptions
AMD Geode™ GX Processors Data Book
Bit
11
10
9
8
7
6
5
4
3
2
Name
P4MDIS
DTCDIS
L2TLBDIS
DCDIS
SPCDEC
WTBRST
WBINVD
NOSMC
NOFWD
BLOCKC
Data Memory Configuration Bit Descriptions (Continued)
Description
Disable 4M PTE Cache.
0: Enable 4M PTEs to be cached. Normal operation.
1: Prevent 4M PTEs from being cached and flush any existing entries.
Disable DTE Cache.
0: Enable DTE cache. Normal operation.
1: Disable DTE cache and flush any existing entries.
Disable L2 TLB. Contents are not modified.
0: Enable L2 TLB. Normal operation.
1: Disable L2 TLB.
Disable Data Memory Cache. Contents are not modified.
0: Enable data memory cache and use standard x86 cacheablility rules. Normal opera-
1: Disable data memory cache. Data cache always generates a miss.
Decrease Number of Speculative Reads of Data Cache.
0: Actively resync cache tag and data arrays so that loads can be speculatively handled
1: Do not attempt to resync cache tag and data arrays.
This is a performance optimization bit and the preferred value may have to be empirically
determined. The cache tag and data arrays get “out of sync” when there is a miss to the
MRU way or if the data array is busy with a store, line fill, or eviction. While the arrays are
out of sync, all hits take two clocks. When they are in sync, hits to the MRU way take one
clock, while hits to other ways take three.
Write-Through Bursting.
0: Writes are sent unmodified to the bus on write-through operations.
1: Writes may be combined using write-burstable semantics on write-through opera-
Convert INVD to WBINVD.
0: INVD instruction invalidates cache without writeback.
1: INVD instruction writes back any dirty cache lines.
Snoop Detecting on Self-Modified Code. Generates snoops on stores for detecting
self-modified code.
0: Generate snoops.
1: Disable snoops.
Forward Data from Bus Controller. Enable forwarding of data directly from BC if a new
request hits a line fill in progress.
0: Forward data from BC if possible.
1: Wait for valid data in cache, then read cache array.
Blocking Cache.
0: New request overlapped with line fill.
1: Line fill must complete before starting new request.
tion.
in one clock if the MRU way is hit.
tions.
31505E
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