AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 411

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

GeodeLink™ Control Processor Register Descriptions
6.10.2.15 GLCP Debug Clock Control (GLCP_DBGCLKCTL)
MSR Address
Type
Reset Value
Note that after the mux to select the clock, a standard clock control gate exists. This register should never be changed from
one non-zero value to another. Always write this register to 0 when moving to an alternative debug clock.
AMD Geode™ GX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
13:11
63:3
Bit
9:1
Bit
2:0
10
0
Name
TST
IN27MHZ
RSVD
DOTRESET
Name
RSVD
CLKSEL
4C000016h
R/W
00000000_00000002h
Description
Reserved. Write as read.
Clock Select. Selects the clock to drive into the debug logic.
000: None.
001: CPU Core clock.
010: GLIU1 clock.
011: DOTCLK.
100: PCI clock.
101-111: Reserved.
Description
Test. These bits control the test signals into the DOTCLK PLL in order to access internal
test points.
27 MHz Input. Needs to be set by software if the input clock is 27 MHz instead of 14.318
MHz. Setting this bit allows VGA clock overrides to work correctly.
Reserved. Write as read.
Dot Clock Reset. The reset pin to the DOTCLK time blocks. The Dot reset is held active
when CHIP_RESET is high, but this bit resets to 0. It is recommended that software set
this bit when changing PLL settings and observe LOCK before releasing this reset.
Unlike the SYS_RSTPLL register, this bit is not required to be set before the other bits in
this register affect the PLL.
GLCP_DOTPLL Bit Descriptions (Continued)
GLCP_DBGCLKCTL Bit Descriptions
GLCP_DBGCLKCTL Register Map
RSVD
RSVD
9
8
31505E
7
6
5
4
3
2
CLKSEL
1
411
0