AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 44

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

3.2.3
44
Signal Name
MA[12:0]
BA0,
BA1
CS0#,
CS1#,
CS2#,
CS3#
RAS0#,
RAS1#
CAS0#,
CAS1#
WE0#,
WE1#
CKE0,
CKE1
DQM0,
DQM1,
DQM2,
DQM3,
DQM4,
DQM5,
DQM6,
DQM7
DQS0,
DQS1,
DQS2,
DQS3,
DQS4,
DQS5,
DQS6,
DQS7
Memory Interface (DDR) Signals (Continued)
Table 3-5 on
Table 3-7 on
CRT: See
TFT: See
page 26.
page 32.
BGD368
31505E
AD26,
AD25,
AA25,
AC23,
AB23,
AD23,
AD18,
AC22,
AE18,
AF23,
AB24
AE24
AC25
AC13
AF24
AF14
Y23,
A23,
D17,
B22,
D25,
K24,
V26,
B15,
B21,
D24,
K23,
U24,
P24
B23
Ball No.
See Table 3-9
on page 38.
BGU396
G24
M26
G26
D13
D26
E23
A23
C16
B23
A17
A10
L26
G4
C7
B3
C2
D2
D7
A4
D3
E4
D5
B4
A9
D1
P2
E3
K2
R1
J1
Type
I/O
O
O
O
O
O
O
O
O
Description
Memory Address Bus. The multiplexed row/column
address lines driven to the system memory.
Supports 256-Mbit SDRAM.
Bank Address Bits. These bits are used to select the
component bank within the SDRAM.
Chip Selects. The chip selects are used to select the
module bank within the system memory. Each chip select
corresponds to a specific module bank.
If CS# is high, the bank(s) do not respond to RAS#,
CAS#, or WE# until the bank is selected again.
Row Address Strobe. RAS#, CAS#, WE#, and CKE are
encoded to support the different SDRAM commands.
RAS0# is used with CS0# and CS1#. RAS1# is used with
CS2# and CS3#.
Column Address Strobe. RAS#, CAS#, WE#, and CKE
are encoded to support the different SDRAM commands.
CAS0# is used with CS0# and CS1#. CAS1# is used with
CS2# and CS3#.
Write Enable. RAS#, CAS#, WE#, and CKE are encoded
to support the different SDRAM commands. WE0# is
used with CS0# and CS1#. WE1# is used with CS2# and
CS3#.
Clock Enable. For normal operation, CKE is held high.
CKE goes low during Suspend. CKE0 is used with CS0#
and CS1#. CKE1 is used with CS2# and CS3#.
Data Mask Control Bits. During memory read cycles,
these outputs control whether the SDRAM output buffers
are driven on the MD bus or not. All DQM signals are
asserted during read cycles.
During memory write cycles, these outputs control
whether or not MD data is written into the SDRAM.
DQM[0] is associated with MD[7:0].
DQM[7] is associated with MD[63:56].
DDR Lower Data Strobe.
AMD Geode™ GX Processors Data Book
Signal Definitions