AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 429

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

GeodeLink™ PCI Bridge Register Descriptions
6.12.1.3
MSR Address
Type
Reset Value
AMD Geode™ GX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:20
15:5
Bit
21
20
19
18
17
16
5
4
GLD SMI MSR (GLD_MSR_SMI)
Name
RSVD (RO)
PARE_ASMI_
FLAG
SYSE_ASMI_
FLAG
VPHE_SSMI_
FLAG
BME_ASMI_
FLAG
TARE_ASMI_
FLAG
MARE_ASMI_
FLAG
RSVD
PARE_ASMI_
EN
SYSE_ASMI_
EN
RSVD
50002002h
R/W
00000000_0000003Fh
Description
Reserved (Read Only). Reads return 0.
Parity Error Event Asynchronous SMI Flag. If high, records that an ASMI was gener-
ated due to detection of a PCI bus parity error. Write 1 to clear; writing 0 has no effect.
PARE_ASMI_EN (bit 5) must be low to generate ASMI and set flag. Additionally, the
PS_ASMI_EN bit (MSR 50002010h[27]) must be set to enable this event.
System Error Event Asynchronous SMI Flag. If high, records that an ASMI was gener-
ated due to the detection of a PCI bus system error. Write 1 to clear; writing 0 has no
effect. SYSE_ASMI_EN (bit 4) must be low to generate ASMI and set flag. Additionally,
the PS_ASMI_EN bit MSR 50002010h[27]) must be set to enable this event.
Virtual PCI Header Event Synchronous SMI Flag. If high, records that an SSMI was
generated due to a flag being set by the Virtual PCI Header support logic. Write 1 to
clear; writing 0 has no effect. VPHE_SSMI_EN (bit 3) must be low to generate SSMI and
set flag.
Broken Master Event Asynchronous SMI Flag. If high, records that an ASMI was gen-
erated due to detection of a broken PCI bus master. Write 1 to clear; writing 0 has no
effect. BM_EN (bit 2) must be low to generate ASMI and set flag. Additionally, the
BM_ASMI_EN bit (MSR 50002010h[26]) must be set to enable this event.
Target Abort Received Event Asynchronous SMI Flag. If high, records that an ASMI
was generated due to reception of a target abort on PCI. Write 1 to clear; writing 0 has no
effect. TAR_EN (bit 1) must be low to generate ASMI and set flag. Additionally, the
TAR_ASMI_EN bit (MSR 50002010h[25]) must be set to enable this event.
Master Abort Received Event (Read/Write-1-to-Clear). If high, records that an ASMI
was generated due to reception of a master abort on PCI. Write 1 to clear; writing 0 has
no effect. MAR_EN (bit 0) must be low to generate ASMI and set flag. Additionally, the
MAR_ASMI bit (MSR 50002010h[24]) must be set to enable this event.
Reserved. Write as read.
Parity Error Event Asynchronous SMI Enable. Write 0 to enable a parity error event to
generate an ASMI and to set flag (bit 21).
System Error Event Asynchronous SMI Enable. Write 0 to enable a system error
event to generate an ASMI and to set flag (bit 20).
GLD_MSR_SMI Bit Descriptions
GLD_MSR_SMI Register Map
RSVD
RSVD
9
8
31505E
7
6
5
4
3
2
1
429
0