AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 214

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

214
63:35
31:10
Bit
9:8
4:0
34
33
32
7
6
5
Name
RSVD
B2B_EN
RSVD
MTEST_EN
RSVD
MASK_CKE[1:0]
CNTL_MSK1
CNTL_MSK0
ADRS_MSK
RSVD
31505E
Description
Reserved. Write as read.
Back-to-back Command Enable. This bit enables/disables the issuing of DRAM com-
mands within back-to-back cycles in both MTEST and normal functional mode. To maxi-
mize performance, this feature should only be disabled in MTEST mode, where the cycle
following the command cycle should be idle for the logic analyzer to be able to properly
capture and interpret the MTEST data.
0: Enable. (Default)
1: Disable.
Reserved. Always write 0.
MTEST Enable. Enables MTEST debug mode, that multiplexes debug data onto the 13
DRAM address output balls one cycle after the command cycle.
0: Disable. (Default)
1: Enable.
Reserved. Write as read.
CKE Mask. Mask output enables for CKE[1:0]. After power-up or warm reset, software
can complete all necessary initialization tasks before clearing this mask to allow commu-
nication with the DRAM. These bits can also be used to selectively mask off the CKE sig-
nal of a DIMM that is not installed.
00: CKE1 and CKE0 unmasked.
01: CKE1 unmasked, CKE0 masked.
10: CKE1 masked, CKE0 unmasked.
11: CKE1 and CKE0 masked. (Default)
Control Mask 1. Mask output enable bit for DIMM1’s CAS1#, RAS1#, WE1#, and
CS[3:2]#.
0: Unmasked. (Default)
1: Masked.
Control Mask 0. Mask output enable bit for DIMM0’s CAS0#, RAS0#, WE0#, and
CS[1:0]#.
0: Unmasked. (Default)
1: Masked.
Address Mask. Mask output enable bit for MA, BA.
0: Unmasked. (Default)
1: Masked.
Reserved. Write as read.
MC_CFCLK_DBUG Bit Descriptions
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