AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 431

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

GeodeLink™ PCI Bridge Register Descriptions
6.12.1.5
MSR Address
Type
Reset Value
AMD Geode™ GX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:35
34:32
15:6
31:6
Bit
Bit
5:4
16
5
4
3
2
1
0
GLD Power Management MSR (GLD_MSR_PM)
Name
MARE_ERR_
FLAG
RSVD (RO)
PARE_ERR_EN
SYSE_ERR_EN
RSVD (RO)
BME_ERR_EN
TARE_ERR_EN
MARE_ERR_
EN
Name
RSVD (RO)
RSVD
RSVD (RO)
PMODE2
50002004h
R/W
00000000_00000000h
Description
Master Abort Received Event Error Flag. If high, records an ERR occurred due to the
reception of a master abort on PCI. Write 1 to clear; writing 0 has no effect. MAR_EN (bit
0) must be low to generate ERR and set flag. Additionally, the MAR_ERR bit (MSR
50002010h[28]) must be set to enable this event.
Reserved (Read Only). Reads return 0.
Parity Error Event Enable. Write 0 to enable a parity error event to generate an ERR
and to set flag (bit 21).
System Error Event Enable. Write 0 to enable a system error event to generate an ERR
and to set flag (bit 20).
Reserved (Read Only). Reads return 0.
Broken Master Event Enable. Write 0 to enable a broken PCI bus master event to gen-
erate an ERR and to set flag (bit 18).
Target Abort Received Event Enable. Write 0 to enable a target abort received event to
generate an ERR and to set flag (bit 17).
Master Abort Received Event Enable. Write 0 to enable a master abort received event
to generate an ERR and to set flag (bit 16).
Description
Reserved (Read Only). Reads as 0.
Reserved. Reads as 0.
Reserved (Read Only). Reads as 0.
Power Mode 2 (Fast-PCI Clock). Power mode for Fast-PCI clock domain.
00: Disable clock gating. Clocks are always on.
01: Enable active hardware clock gating. Clock goes off whenever this module’s circuits
10: Reserved.
11: Reserved.
are not busy.
GLD_MSR_ERROR Bit Descriptions
GLD_MSR_PM Bit Descriptions
GLD_MSR_PM Register Map
RSVD
RSVD
9
8
31505E
7
6
5
4
3
2
1
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0