AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 63

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

GeodeLink™ Inteface Unit Register Descriptions
AMD Geode™ GX Processors Data Book
31:15
Bit
42
41
40
39
38
37
36
35
34
33
32
14
Name
RQCOMP3_
ERR_FLAG
RQCOMP2_
ERR_FLAG
RQCOMP1_
ERR_FLAG
RQCOMP0_
ERR_FLAG
STATCNT3_
ERR_FLAG
STATCNT2_
ERR_FLAG
STATCNT1_
ERR_FLAG
STATCNT0_
ERR_FLAG
SSMI_ERR_
FLAG
UNEXP_ADDR_
ERR_FLAG
UNEXP_TYPE_
ERR_FLAG
RSVD
DACOMP3_
ERR_EN
Description
Request Comparator 3 Error Flag. If high, records that an ERR was generated due to a
Request Comparator 3 (RQ_COMPARE_VAL3, GLIU0 MSR 100000C6h, GLIU1 MSR
400000C6h) event. Write 1 to clear; writing 0 has no effect. RQCOMP3_ERR_EN (bit 10)
must be low to generate ERR and set flag.
Request Comparator 2 Error Flag. If high, records that an ERR was generated due to a
Request Comparator 2 (RQ_COMPARE_VAL2, GLIU0 MSR 100000C4h, GLIU1 MSR
400000C4h) event. Write 1 to clear; writing 0 has no effect. RQCOMP2_ERR_EN (bit 9)
must be low to generate ERR and set flag.
Request Comparator 1 Error Flag. If high, records that an ERR was generated due to a
Request Comparator 1 (RQ_COMPARE_VAL1, GLIU0 MSR 100000C2h, GLIU1 MSR
400000C2h) event. Write 1 to clear; writing 0 has no effect. RQCOMP1_ERR_EN (bit 8)
must be low to generate ERR and set flag.
Request Comparator 0 Error Flag. If high, records that an ERR was generated due to a
Request Comparator 0 (RQ_COMPARE_VAL0, GLIU0 MSR 100000C0h, GLIU1 MSR
400000C0h) event. Write 1 to clear; writing 0 has no effect. RQCOMP0_ERR_EN (bit 7)
must be low to generate ERR and set flag.
Statistic Counter 3 Error Flag. If high, records that an ERR was generated due to a
Statistic Counter 3 (GLIU0 MSR 100000ACh, GLIU1 MSR 400000ACh) event. Write 1 to
clear; writing 0 has no effect. STATCNT3_ERR_EN (bit 6) must be low to generate ERR
and set flag.
Statistic Counter 2 Error Flag. If high, records that an ERR was generated due to a
Statistic Counter 2 (GLIU0 MSR 100000A8h, GLIU1 MSR 400000A8h) event. Write 1 to
clear; writing 0 has no effect. STATCNT2_ERR_EN (bit 5) must be low to generate ERR
and set flag.
Statistic Counter 1 Error Flag. If high, records that an ERR was generated due to a
Statistic Counter 1 (GLIU0 MSR 100000A4h, GLIU1 MSR 400000A4h) event. Write 1 to
clear; writing 0 has no effect. STATCNT1_ERR_EN (bit 4) must be low to generate ERR
and set flag.
Statistic Counter 0 Error Flag. If high, records that an ERR was generated due to a
Statistic Counter 0 (GLIU0 MSR 100000A0h, GLIU1 MSR 400000A0h) event. Write 1 to
clear; writing 0 has no effect. STATCNT0_ERR_EN (bit 3) must be low to generate ERR
and set flag.
SSMI Error Flag. If high, records that an ERR was generated due an unhandled SSMI
(synchronous error). Write 1 to clear; writing 0 has no effect. SSMI_ERR_EN (bit 2) must
be low to generate ERR and set flag.
Unexpected Address Error Flag. If high, records that an ERR was generated due an
unexpected address (synchronous error). Write 1 to clear; writing 0 has no effect.
UNEXP_ADD_ERR_EN (bit 1) must be low to generate ERR and set flag.
Unexpected Type Error Flag. If high, records that an ERR was generated due an unex-
pected type (synchronous error). Write 1 to clear; writing 0 has no effect.
UNEXP_TYPE_ERR_EN (bit 0) must be low to generate ERR and set flag.
Reserved. Write as read.
Data Comparator 3 Error Enable. Write 0 to enable DACOMP3_ERR_FLAG (bit 46)
and to allow a Data Comparator 3
(DA_COMPARE_VAL_LO3/DA_COMPARE_VAL_HI3, GLIU0 MSR
100000DCh/100000DDh, GLIU1 MSR 400000DCh/400000DDh) event to generate an
ERR and set flag.
GLD_MSR_ERROR Bit Descriptions (Continued)
31505E
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