AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 317

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

Display Controller Register Descriptions
6.6.13.8
GC Index
Type
Reset Value
AMD Geode™ GX Processors Data Book
Bit
1:0
7
6
5
4
3
2
Graphics Mode
Name
RSVD
256_CM
SH_R_MD
ODD_EVEN
RD_MD
RSVD
WR_MD
05h
R/W
xxh
Description
Reserved
256 Color Mode. When set to a 1, this bit configures the video serializers in the graphics
controller for the 256 color mode (BIOS mode 13h). When this bit is 0, the Shift Register
Mode bit (bit 5) controls the serializer configuration.
Shift Register Mode. When set to a 1, this bit configures the video serializers for BIOS
modes 4 and 5. When this bit is 0, the serializers are taken in parallel (i.e., configured for
4-bit planar mode operation).
Note that the serializers are also wired together serially so that Map 3 bit 7 feeds Map 2
bit 0, Map 2 bit 7 feeds Map 1 bit 0, and Map 1 bit 7 feeds Map 0 bit 0. This allows for a
32-pixel 1 bit-per-pixel serializer to be used. For this configuration, color planes 1, 2, and
3 should be masked off using the Color Plane Enable register (AC Index 12h[3:0]).
Odd/Even. When this bit is set to 1, CPU address bit A0 select between Maps 0 and 1 or
Maps 2 and 3, depending on the state of the Read Map Select field (GC Index 04h[1:0]).
When this bit is 0, the CPU accesses data sequentially within a map. This bit is equiva-
lent to the Odd/Even bit in the Miscellaneous Register (GC Index 06h[1]), but is inverted
in polarity from that bit.
Read Mode. This bit determines what is returned to the CPU when it reads the frame
buffer. When this bit is 1, the result of a color compare operation is returned. The 8 bits in
the CPU read data contain a 1 in each pixel position where the color compare operation
was true, and a 0 where the operation was false. When this bit is 0, frame buffer map
data is returned.
0: Read Mode 0.
1: Read Mode 1.
Reserved. Write as read.
Write Mode. This field specifies how CPU data is written to the frame buffer. Note that
the Write Operation field in the Data Rotate register (GC Index 03h[4:3]) specifies how
CPU data is combined with data in the data latches for Write Mode 0, Write Mode 2, and
Write Mode 3.
00: Write Mode 0: CPU data is rotated by the count in the Data Rotate register (GC
01: Write Mode 1: Each map enabled by the Map Mask Register (SQ 02h[3:0]) is written
10: Write Mode 2: CPU data is replicated for each map and combined with the data
11: Write Mode 3: Each map is written with its corresponding Set/Reset bit replicated
Graphics Mode Register Bit Descriptions
Index 03h[4:3]). Each map enabled by the Map Mask Register (SQ 02h[3:0]) is writ-
ten by the rotated CPU data combined with the latch data (if set/reset is NOT
enabled for that map, GC Index 00h[3:0]) or by the map’s corresponding set/reset bit
replicated across the 8-bit byte (if set/reset IS enabled for that map). The Bit Mask
Register (GC Index 08h) is used to protect individual bits in each map from being
updated.
with its corresponding byte in the data latches.
latches and written to memory. The Bit Mask register (GC Index 08h) is used to pro-
tect individual bits in each map from being updated.
through a byte (Enable Set/Reset is ignored, GC Index 02h[3:0]). The CPU data is
rotated and ANDed with the Bit Mask register (GC Index 08h). The resulting mask is
used to protect individual bits in each map.
31505E
317