AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 483

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

Electrical Specifications
Note 1. Refer to Figure 7-8 "DDR Write Timing Measurement Points" on page 484 and Figure 7-9 "DDR Read Timing Mea-
Note 2. The even and odd clocks are an inversion of each other (differential clocking).
Note 3. 0.5 ns max t
Note 4. 1.3 ns < t
Note 5. -0.7 ns < t
Note 6. DQS output preamble and postamble timings are affected by the SD_FB_CLK duty cycle.
Note 7. The MD timing relative to DQS are on a per-byte basis only. MD[7:0] and DQM[0] must be measured against
AMD Geode™ GX Processors Data Book
Symbol
(Note 1)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CK
SKEW1
DEL1
DQSCK
SKEW2
DEL2
RPRE
RPST
WPRE
WPST
DQSQs
DQSQh
VAL1
VAL2
surement Points" on page 484.
DQS[0], and MD[15:8] and DQM[1] must be measured against DQS[1], etc.
Parameter
SD_FB_CLK Output Clock Period
SD_FB_CLK Output Duty Cycle
SDCLK[5:0], SDCLK[5:0]# Period
SDCLK[5:0], SDCLK[5:0]# Duty cycle
SDCLK[n] to SDCLK[n]x Skew (n = 0.5)
SDCLK[5:0], SDCLK[5:0]# Edge Delay from
SD_FB_CLK
DQS[7:0] Input and Output Period
DQS[7:0] Input and Output Duty Cycle
DQS[7:0] Input Delay relative to SD_FB_CLK
DQS-to-DQS Input Skew
DQS[7:0] Output Edge Delay from SD_FB_CLK
DQS Input Preamble before first DQS rising
edge
DQS Input Postamble after last DQS
DQS Output Write Preamble Valid Time before
DQS rising edge
DQS Output Write Postamble after last DQS fall-
ing edge
MD[63:0] Input Setup Time before DQS edge
MD[63:0] Input Hold Time after DQS edge
MD[63:0], DQM[7:0] Output Data Valid Delay
time from DQS rising or falling edge
MA[12:0], BA[1:0], CAS[1:0]#, RAS[1:0]#,
CKE[1:0], CS[3:0]#, WE[1:0] Output Valid Delay
Time from SD_FB_CLK
VAL2
DEL2
DEL1
- t
- t
DEL1
DEL1
does not occur under same conditions as 1 ns min t
< 4.5 ns
< 0.7 ns
Table 7-14. SDRAM Interface Signals
0.25*t
0.5*t
0.5*t
0.35
Min
-0.7
-0.5
-1.0
7.5
7.5
7.5
0.5
CK
0.9
1.0
CK
-2
CK
-1.75
+0.35
-1
45/55
45/55
45/55
VAL2
0.5*t
0.5*t
0.5*t
.
Max
CK
0.1
0.5
0.7
4.5
CK
4
3
CK
+1.75
-1.25
+1
31505E
Unit
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%
CK
CK
Comments
Note 2
Note 2
Guaranteed by
design
Note 3, Note 4
Note 5
Note 6
Note 6
Note 7
,
Note 7
Note 7
Note 3, Note 4
483