AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 354

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

6.8.3.8
VP Memory Offset 038h
Type
Reset Value
6.8.3.9
VP Memory Offset 040h
Type
Reset Value
354
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:24
63:8
23:0
Bit
7:0
Bit
Gamma Address (GAR)
Gamma Data (GDR)
Name
RSVD (RO)
GAM_ADDR
Name
RSVD (RO)
GAM_DATA
RSVD
R/W
00000000_000000xxh
R/W
00000000_00xxxxxxh
31505E
Description
Reserved (Read Only). Reads back as 0.
Gamma Address. Specifies the address to be used for the next access to the Gamma
Data register (VP Memory Offset 040h[23:0]). Each access to the Data register automat-
ically increments the Gamma Address register. If non-sequential access is made to the
Gamma, the Address register must be loaded between each non-sequential data block.
Description
Reserved (Read Only). Reads back as 0.
Gamma Data. Contains the read or write data for a Gamma Correction RAM.
Provides the Gamma data. The data can be read or written to the Gamma Correction
RAM via this register. Prior to accessing this register, an appropriate address should be
loaded to the Gamma Address register (VP Memory Offset 038h[7:0]). Subsequent
accesses to the Gamma Data register cause the internal address counter to be incre-
mented for the next cycle.
Note:
When a read or write to the Gamma Correction RAM occurs, the previous output
value is held for one additional DOTCLK period. This effect should go unnoticed
during normal operation.
RSVD
GAR Bit Descriptions
GDR Bit Descriptions
GAR Register Map
GDR Register Map
RSVD
RSVD
GAM_DATA
AMD Geode™ GX Processors Data Book
Video Processor Register Descriptions
9
9
8
8
7
7
6
6
5
5
GAM_ADDR
4
4
3
3
2
2
1
1
0
0