AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 277

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

Display Controller Register Descriptions
6.6.4.6
DC Memory Offset 24h
Type
Reset Value
This register specifies the offset at which the video U (YUV 4:2:0) buffer starts.
6.6.4.7
DC Memory Offset 28h
Type
Reset Value
This register specifies the offset at which the video V (YUV 4:2:0) buffer starts.
AMD Geode™ GX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:28
31:28
27:0
27:0
Bit
Bit
RSVD
RSVD
DC Video U Buffer Start Address Offset (DC_VID_U_ST_OFFSET)
DC Video V Buffer Start Address Offset (DC_VID_V_ST_OFFSET)
Name
RSVD
OFFSET
Name
RSVD
OFFSET
R/W
00000000h
R/W
00000000h
Description
Reserved. Write as read.
Video U Buffer Start Offset. This value represents the starting location for the video U
buffer. The lower three bits should always be programmed as zero so that the start offset
is aligned to a QWORD boundary. A buffer for U data is only used if YUV 4:2:0 display
mode is selected (DC Memory Offset 04h[20] = 1).
Description
Reserved. Write as read.
Video V Buffer Start Offset. This value represents the starting location for the video V
buffer. The lower three bits should always be programmed as zero so that the start offset
is aligned to a QWORD boundary. A buffer for V data is only used if YUV 4:2:0 display
mode is selected (DC Memory Offset 04h[20] = 1).
DC_VID_U_ST_OFFSET Bit Descriptions
DC_VID_V_ST_OFFSET Bit Descriptions
DC_VID_U_ST_OFFSET Register Map
DC_VID_V_ST_OFFSET Register Map
OFFSET
OFFSET
9
9
8
8
31505E
7
7
6
6
5
5
4
4
3
3
2
2
0h
0h
1
1
277
0
0