AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 288

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

6.6.7.2
DC Memory Offset 74h
Type
Reset Value
This register contains the data for a palette access cycle. When a read or write to the palette RAM occurs, the previous out-
put value is held for one additional DOTCLK period. This effect goes unnoticed and provides for sparkle-free update. Prior
to a read or write to this register, the DC_PAL_ADDRESS register (DC Memory Offset 70h[8:0] must be loaded with the
appropriate address. The address automatically increments after each access to this register, so for sequential access, the
address register need only be loaded once.
If the SGRE bit in DC_GENERAL_CFG is set (DC Memory Offset 04h[25] = 1), this register reads back the state of the
graphics output pixel stream signature.
6.6.7.3
DC Memory Offset 78h
Type
Reset Value
This register is provided to enable testability of the display FIFO RAM. Before it is accessed, the DIAG bit in the
DC_GENERAL_CFG register should be set high (DC Memory Offset 04h[28] = 1) and the DFLE bit should be set low (DC
Memory Offset 04h[0] = 0). Since each FIFO entry is 64 bits, an even number of write operations should be performed.
Each pair of write operations causes the FIFO write pointer to increment automatically. After all write operations have been
performed, a pair of reads of don't care data must be performed to load 64-bits of data into the output latch. Each subse-
quent read contains the appropriate data that was previously written. Each pair of read operations causes the FIFO read
pointer to increment automatically.
This register is also used for writing to the compressed line buffer. Each pair of writes to this register stores a 64-bit data
value that is used for the next write to the compressed line buffer. The write pulse to the compressed line buffer is gener-
ated by writing dummy data to the DC_PAL_DATA register (DC Memory Offset 74h[23:0]) while in DIAG mode.
288
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:24
23:0
31:0
Bit
Bit
DC Palette Data (DC_PAL_DATA)
DC Display FIFO Diagnostic (DC_DFIFO_DIAG)
Name
RSVD
PAL_DATA
Name
DFIFO_DATA
RSVD
R/W
xxxxxxxxh
R/W
xxxxxxxxh
31505E
Description
Reserved. Write as read.
PAL Data. This 24-bit field contains the read or write data for a palette access. If the
SGRE bit in DC_GENERAL_CFG is set (DC Memory Offset 04h[25] = 1), a read to this
register reads back the state of the graphics output pixel stream signature.
Description
Display FIFO Diagnostic Read or Write Data
DC_DFIFO_DIAG Bit Descriptions
DC_PAL_DATA Bit Descriptions
DC_DFIFO_DIAG Register Map
DC_PAL_DATA Register Map
DFIFO_DATA
PAL_DATA
AMD Geode™ GX Processors Data Book
Display Controller Register Descriptions
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0