AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 239

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

Graphics Processor Register Descriptions
6.4.2.9
GP Memory Offset 18h
Type
Reset Value
In solid pattern mode, the pattern hardware is disabled and GP_PAT_COLOR_0 is selected as the input to the raster oper-
ation.
In monochrome pattern mode, GP_PAT_COLOR_0 and GP_PAT_COLOR_1 are used for expanding the monochrome
pattern into color. A clear bit in the pattern is replaced with the color stored in GP_PAT_COLOR_0 and a set bit in the pat-
tern is replaced with the color stored in GP_PAT_COLOR_1.
In color pattern mode, these registers each hold part of the pattern according to the Table 6-25.
These registers should only be written after setting the bpp (bits [31:30]) and PM (bits in [9:8]) GP_RASTER_MODE (GP
Memory Offset 38h), since the value written may be replicated if necessary to fill the register. If the pattern is color, no rep-
lication is performed and the data is written to the registers exactly as it is received. If the pattern is monochrome, the write
data is expanded if the color depth is less than 32 bpp. Thus a write to these registers in 8-bpp monochrome pattern mode
takes the least significant data byte and replicates it in the four bytes of the register. In 16-bpp monochrome pattern mode,
the least significant two bytes are replicated in the upper half of the register. A read returns the replicated data.
AMD Geode™ GX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Note: Registers GP_PAT_COLOR_2 - GP_PAT_COLOR_5 are not pipelined. They should not be written to when the
31:0
Bit
GP_PAT_COLOR_0
GP_PAT_COLOR_1
GP_PAT_COLOR_2
GP_PAT_COLOR_3
GP_PAT_COLOR_4
GP_PAT_COLOR_5
"BLT Busy" bit is set in the GP_BLT_STATUS register (GP Memory Offset 44h[0]), which indicates that a BLT is
in progress. Writing to these registers when a BLT is active or pending can corrupt that operation.
Pattern Color (GP_PAT_COLOR_x)
Name
PAT_COLOR_x
Register
1Ch
20h
24h
28h
2Ch
R/W
00000000h
GP_PAT_COLOR_0
GP_PAT_COLOR_1
GP_PAT_COLOR_2
GP_PAT_COLOR_3
GP_PAT_COLOR_4
GP_PAT_COLOR_5
Table 6-25. PAT_COLOR Usage for Color Patterns
Description
Pattern Color x.
Mono pattern mode - Pattern color for expansion.
Color pattern mode - Color pattern.
GP_PAT_COLOR_x Bit Descriptions
GP_PAT_COLOR_x Register Map
Line 1, pixels 3-0
Line 1, pixels 7-4
Line 2, pixels 3-0
Line 2, pixels 7-4
Line 3, pixels 3-0
Line 3, pixels 7-4
8-bpp Mode
PAT_COLOR_x
Line 0, pixels 5-4
Line 0, pixels 7-6
Line 1, pixels 1-0
Line 1, pixels 3-2
Line 1, pixels 5-4
Line 1, pixels 7-6
16-bpp Mode
9
8
31505E
7
6
5
32-bpp Mode
Line 0, pixel 2
Line 0, pixel 3
Line 0, pixel 4
Line 0, pixel 5
Line 0, pixel 6
Line 0, pixel 7
4
3
2
1
239
0