AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 521

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

Instruction Set
AMD Geode™ GX Processors Data Book
F2XM1 Function Evaluation 2x-1
FABS Floating Absolute Value
FADD Floating Point Add
FADDP Floating Point Add, Pop
FIADD Floating Point Integer Add
FCHS Floating Change Sign
FCLEX Clear Exceptions
FNCLEX Clear Exceptions
FCMOVB Floating Point Conditional Move if Below
FCMOVE Floating Point Conditional Move if Equal
FCMOVBE Floating Point Conditional Move if
FCMOVU Floating Point Conditional Move if
FCMOVNB Floating Point Conditional Move if
FCMOVNE Floating Point Conditional Move if
FCMOVNBE Floating Point Conditional Move if
FCMOVNU Floating Point Conditional Move if
FCOM Floating Point Compare
FCOMP Floating Point Compare, Pop
FCOMPP Floating Point Compare, Pop
FCOMI Floating Point Compare Real and Set EFLAGS
FCOMIP Floating Point Compare Real and Set EFLAGS, Pop
FUCOMI Floating Point Unordered Compare Real and Set EFLAGS
FUCOMIP Floating Point Unordered Compare Real and Set EFLAGS, Pop
FICOM Floating Point Integer Compare
FICOMP Floating Point Integer Compare, Pop
FCOS Function Evaluation: Cos(x)
Top of Stack
80-bit Register
64-bit Real
32-bit Real
32-bit integer
16-bit integer
Unordered
Not Below
Not Equal
Not Below or Equal
Not Unordered
80-bit Register
64-bit Real
32-bit Real
80-bit Register
64-bit Real
32-bit Real
Two Stack Elements
80-bit Register
80-bit Register
80-bit Integer
80-bit Integer
32-bit integer
16-bit integer
32-bit integer
16-bit integer
Below or Equal
FPU Instruction
D9 F0
D9 E1
DC [1100 0 n]
D8 [1100 0 n]
DC [mod 000 r/m]
D8 [mod 000 r/m]
DE [1100 0 n]
DA [mod 000 r/m]
DE [mod 000 r/m]
D9 E0
(9B) DB E2
DB E2
DA [1100 0 n]
DA [1100 1 n]
DA [1101 0 n]
DA [1101 1 n]
DB [1100 0 n]
DB [1100 1 n]
DB [1101 0 n]
DB [1101 1 n]
D8 [1101 0 n]
DC [mod 010 r/m]
D8 [mod 010 r/m]
D8 [1101 1 n]
DC [mod 011 r/m]
D8 [mod 011 r/m]
DE D9
DB [1111 0 n]
DF [1111 0 n]
DB [1110 1 n]
DF [1110 1 n]
DA [mod 010 r/m]
DE [mod 010 r/m]
DA [mod 011 r/m]
DE [mod 011 r/m
D9 FF
Table 8-29. FPU Instruction Set
Opcode
TOS <--- 2
TOS <--- | TOS |
ST(n) <--- ST(n) + TOS
TOS <--- TOS + ST(n)
TOS <--- TOS + M.DR
TOS <--- TOS + M.SR
ST(n) <--- ST(n) + TOS; then pop TOS
TOS <--- TOS + M.SI
TOS <--- TOS + M.WI
TOS <--- - TOS
Wait then Clear Exceptions
Clear Exceptions
If (CF=1) ST(0) <--- ST(n)
If (ZF=1) ST(0) <--- ST(n)
If (CF=1 or ZF=1) ST(0) <--- ST(n)
If (PF=1) ST(0) <--- ST(n)
If (CF=0) ST(0) <--- ST(n)
If (ZF=0) ST(0) <--- ST(n)
If (CF=0 and ZF=0) ST(0) <--- ST(n)
If (PF=0) ST(0) <--- ST(n)
CC set by TOS - ST(n)
CC set by TOS - M.DR
CC set by TOS - M.SR
CC set by TOS - ST(n); then pop TOS
CC set by TOS - M.DR; then pop TOS
CC set by TOS - M.SR; then pop TOS
CC set by TOS - ST(1); then pop TOS and ST(1)
EFLAG set by TOS - ST(n)
EFLAG set by TOS - ST(n); then pop TOS
EFLAG set by TOS - ST(n)
EFLAG set by TOS - ST(n); then pop TOS
CC set by TOS - M.WI
CC set by TOS - M.SI
CC set by TOS - M.WI; then pop TOS
CC set by TOS - M.SI; then pop TOS
TOS <--- COS(TOS)
TOS
-1
Operation
31505E
(or extended)
Sngle/Dbl
145 - 166
146 - 215
Clock Ct
1/6
1/6
1/6
1/6
1/6
2/7
2/7
1/6
1/6
1/6
1/6
1/6
1/6
1/6
1/6
1/6
1/6
1/6
2/7
2/7
2/7
2/7
1+
1+
1
1
1
1
1
1
1
1
1
1
Notes
2
3
2
2
3
3
3
3
3
3
3
3
1
521