AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 283

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

Display Controller Register Descriptions
6.6.5.5
DC Memory Offset 54h
Type
Reset Value
This register contains vertical blank timing information. All values are specified in lines. For interlaced display, no border is
supported, so blank timing is implied by the total/active timing.
6.6.5.6
DC Memory Offset 58h
Type
Reset Value
This register contains vertical sync timing information. All values are specified in lines.
AMD Geode™ GX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:27
26:16
15:11
31:27
26:16
15:11
10:0
10:0
Bit
Bit
RSVD
RSVD
DC CRT Vertical Blank Timing (DC_V_BLANK_TIMING)
DC CRT Vertical Sync Timing (DC_V_SYNC_TIMING)
Name
RSVD
V_BLANK_END
RSVD
V_BLANK_ST
Name
RSVD
V_SYNC_END
RSVD
V_SYNC_ST
R/W
xxxxxxxxh
R/W
xxxxxxxxh
Description
Reserved. Write as 0.
Vertical Blank End. This field represents the line at which the vertical blanking signal
becomes inactive minus 1. If the display is interlaced, no border is supported, so this
value should be identical to V_TOTAL (DC Memory Offset 50h[26:16]).
Reserved. Write as 0.
Vertical Blank Start. This field represents the line at which the vertical blanking signal
becomes active minus 1. If the display is interlaced, this value should be programmed to
V_ACTIVE (DC Memory Offset 50h[10:0])plus 1.
Description
Reserved. Write as 0.
Vertical Sync End. This field represents the line at which the CRT vertical sync signal
becomes inactive minus 1.
Reserved. Write as 0.
Vertical Sync Start. This field represents the line at which the CRT vertical sync signal
becomes active minus 1. For interlaced display, note that the vertical counter is incre-
mented twice during each line and since there is an odd number of lines, the vertical sync
pulse triggers in the middle of a line for one field and at the end of a line for the subse-
quent field.
V_BLANK_END
V_SYNC_END
DC_V_BLANK_TIMING Bit Descriptions
DC_V_SYNC_TIMING Bit Descriptions
DC_V_BLANK_TIMING Register Map
DC_V_SYNC_TIMING Register Map
RSVD
RSVD
9
9
8
8
31505E
7
7
V_BLANK_ST
V_SYNC_ST
6
6
5
5
4
4
3
3
2
2
1
1
283
0
0