AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 406

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

6.10.2.13 GLCP System Reset and PLL Control (GLCP_SYS_RSTPLL)
MSR Address
Type
Reset Value
This register is initialized during POR, but otherwise is not itself reset by any “soft-reset” features. Note that although all
PLL and timing control bits can be written and read back the last written data, none of the frequency control bit writes take
effect on the system until CHIP_RESET (bit 0) is set (MDIV, VDIV, FBDIV, BYPASS, TST, DDRMODE,
VA_SEMI_SYNC_MODE, PCI_SEMI_SYNC_MODE). Writing this register with the CHIP_RESET bit set never sends a
write-response over GLIU1. (This allows halting bus traffic before the reset occurs.) Writing to the PD or RESET bits has an
immediate effect.
406
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:45
44:41
40:38
37:32
31:26
Bit
25
24
SWFLAGS
Name
RSVD
MDIV
VDIV
FBDIV
SWFLAGS
LOCK (RO)
LOCKWAIT
4C000014h
R/W
xxxxxxxx_00xxxxxxh
31505E
Description
Reserved. Write as read.
GLIU1 Divisor. The divider for the GLIU1 clock.
0000: Divide by 2, ... ,
1111: Divide by 17.
These bits are read/write but the actual clock divider control is only changed when
CHIP_RESET (bit 0) is also set.
CPU Core Divisor. The divider setting for the CPU Core clock.
000: Divide by 2 (Default), ...,
111: Divide by 9.
These bits are read/write but the actual clock divider control is only changed when
CHIP_RESET (bit 0) is also set.
Feedback Divisor. The feedback divider setting for the system PLL are pseudo-random
due to the design of the high-speed PLL divider (see Table 6-60 "FBDIV Setting for
Desired PLL Divider Results" on page 409 for decode). These bits are read/write but the
actual PLL control is only changed when CHIP_RESET (bit 0) is also set.
Software Flags. Flags that are reset only by the POR# signal, not the CHIP_RESET.
They are reset to 0 and can be used as flags in the boot code that survive CHIP_RESET.
Lock (Read Only). Lock signal from the system PLL.
Lock Wait. Allow the chip to release reset when the PLL lock signal is set.
0: Disable (Default).
1: Enable.
RSVD
GLCP_SYS_RSTPLL Bit Descriptions
HOLD_COUNT
GLCP_SYS_RSTPLL Register Map
GeodeLink™ Control Processor Register Descriptions
TST
MDIV
AMD Geode™ GX Processors Data Book
9
8
VDIV
7
6
5
4
FBDIV
3
2
1
0