AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 407

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

GeodeLink™ Control Processor Register Descriptions
AMD Geode™ GX Processors Data Book
23:16
12:11
Bit
6:4
15
14
13
10
9
8
7
3
Name
HOLD_COUNT
BYPASS
PD
RESETPLL
RSVD
DDRMODE
VA_SEMI_
SYNC_MODE
PCI_SEMI_
SYNC_MODE
DSTALL (RO)
BOOTSTRAP_
STAT (RO)
DOTPOSTDIV3
GLCP_SYS_RSTPLL Bit Descriptions (Continued)
Description
Hold Count. The number of PLL reference clock cycles (multiply by 16) that the PLL is
powered down for and also the number before releasing CHIP_RESET (bit 0). (LOCK-
WAIT can cause reset to release earlier, but this timeout allows the releasing of reset if
lock is not achieved in a certain period).
00000000: Wait 0 clock cycles (Default).
00000001: Wait 1*16 clock cycles....
11111111: Wait 16*255 clock cycles.
PLL Bypass. The POR value in this register is undefined. After POR, DOTREF is used
for the CPU Core clock and GLIU clock. For normal operation of the system PLL, this bit
must be written to 0 before CHIP_RESET (bit 0) operation.
0: After CHIP_RESET is performed, the output of the system PLL is used for the CPU
1: After CHIP_RESET is performed, DOTREF is used for the CPU Core clock and GLIU
Power Down. This signal controls the power down mode of the system PLL. It is active
high. It has an immediate effect, so it is not recommended unless either BYPASS (bit 15)
is set or CHIP_RESET (bit 0) is set. This bit is always cleared by a CHIP_RESET.
PLL Reset. This signal resets the voltage control setting of the voltage-controlled oscilla-
tor on the system PLL. This potentially allows lock to be acquired in the case that the PLL
itself has intermittent behavior. It is active high. It has an immediate effect, so it is not rec-
ommended unless either BYPASS (bit 15) is set or CHIP_RESET (bit 0) is set. This bit is
always cleared by a CHIP_RESET.
Reserved.
DDR Mode.
0: The output pads of the GLMC are configured for DDR communication and the its con-
1: Reserved.
Synchronous CPU Core and GLIU1. This bit controls whether the CPU Core processor
uses a FIFO for interfacing with GLIU1 or not. If the bit is high, the CPU Core does not
use the FIFO; it behaves as if the CPU Core and GLIU1 domains were synchronous.
This bit can be set high as long as the CPU Core and GLIU1 frequencies are multiples of
each other. The bit always resets low. This bit is read/writable but the actual signal to the
CPU Core is only changed when CHIP_RESET (bit 0) is also set.
Synchronous CPU Core and GLIU1. This bit controls whether the PCI uses the falling
edges of MB_FUNC_CLK and PCI_FUNC_CLK for interfacing with GLIU1 or not. If the
bit is high, PCI does not use falling clock edges; it behaves as if the CPU Core and
GLIU1 domains were synchronous. This bit can be set high as long as the PCI and
GLIU1 frequencies are multiples of each other. The bit always resets low. This bit is
read/writable but the actual signal to the PCI block is only changed when CHIP_RESET
(bit 0) is also set.
Debug Stall (Read Only). A 1 indicates that the system booted up stalled. This register
is initialized by IRQ13 strapping at POR. IRQ13 should be pulled low for normal opera-
tion.
Bootstrap Status (Read Only). These bits are initialized by GNT[3:0]# respectively at
POR. No additional hardware action occurs from the GNT# straps.
DOTPLL Post-Divide by 3. This read/writable bit has an immediate effect on the DOT-
PLL behavior. It post-divides the PLL output frequency by three. Refer to the
GLCP_DOTPLL register for details.
core clock and CLIU clock.
clock.
trol logic is clocked with a clock running at half of the GLIU1 frequency. This bit is
read/writable but the actual memory frequency is only changed when CHIP_RESET
(bit 0) is also set.
31505E
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