AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 499
AGXD533AAXF0CC
Manufacturer Part Number
AGXD533AAXF0CC
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.AGXD533AAXF0CC.pdf
(539 pages)
Specifications of AGXD533AAXF0CC
Device Core
X86
Device Core Size
64b
Frequency (max)
400MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5V
Operating Supply Voltage (max)
1.58V
Operating Supply Voltage (min)
1.42V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
368
Package Type
BGD
Lead Free Status / Rohs Status
Not Compliant
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Instruction Set
8.3
The instruction set for the Geode GX processor core is
summarized in Table 8-26. The table uses several symbols
and abbreviations that are described next and listed in
Table 8-25.
8.3.1
Opcodes are given as hex values except when they appear
within brackets as binary values.
8.3.2
The clock counts listed in the instruction set summary table
(Table 8-26) are grouped by operating mode (real and pro-
AMD Geode™ GX Processors Data Book
Opcode
Clock Count
Flags
OF
Abbreviation
Symbol or
+++
###
DF
CF
TF
SF
ZF
AF
PF
##
IF
#
+
n
L
0
1
u
x
/
\
-
|
Processor Core Instruction Set
Opcodes
Clock Counts
Description
Immediate 8-bit data.
Immediate 16-bit data.
Full immediate 32-bit data (8, 16, or 32 bits).
8-bit signed displacement.
Full signed displacement (16 or 32 bits).
Register operand/memory operand.
Number of times operation is repeated.
Level of the stack frame.
Conditional jump taken | Conditional jump not taken. (e.g., “4|1” = four clocks if jump taken, one clock
if jump not taken).
CPL ≤ IOPL \ CPL > IOPL (where CPL = Current Privilege Level, IOPL = I/O Privilege Level).
Overflow Flag.
Direction Flag.
Interrupt Enable Flag.
Trap Flag.
Sign Flag.
Zero Flag.
Auxiliary Flag.
Parity Flag.
Carry Flag.
Flag is modified by the instruction.
Flag is not changed by the instruction.
Flag is reset to “0.”
Flag is set to “1.”
Flag is undefined following execution of the instruction.
Table 8-25. Processor Core Instruction Set Table Legend
tected) and whether there is a register/cache hit or a cache
miss. In some cases, more than one clock count is shown
in a column for a given instruction, or a variable is used in
the clock count.
8.3.3
There are nine flags that are affected by the execution of
instructions. The flag names have been abbreviated and various
conventions used to indicate what effect the instruction has
on the particular flag.
Flags
31505E
499
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