AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 271

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

Display Controller Register Descriptions
AMD Geode™ GX Processors Data Book
22:21
15:12
11:8
Bit
23
20
19
18
17
16
7
Name
VFSL
RSVD
YUVM
VDSE
VGAFT
FDTY
STFM
DFHPEL
DFHPSL
VGAE
DC_GENERAL_CFG Bit Descriptions (Continued)
Description
Video FIFO Select. This bit determines how the Display Controller's memory interface
behaves when fetching video data. When 0, the Display Controller attempts to fetch
video data whenever there is room for 32 bytes (one cacheline) of video data in the
DFIFO. When set to 1, the Display Controller waits until 64 bytes of space is available.
Reserved.
YUV Mode. Selects YUV display mode.
0: YUV 4:2:2 display mode.
1: YUV 4:2:0 display mode.
Video Downscale Enable.
0: Send all video lines to the display filter.
1: Use DC_VID_DS_DELTA (DC Memory Offset 80h[31:18]) as a DDA delta value to
VGA Fixed Timing. When in VGA mode (VGAE, bit 7 = 1), this bit indicates that the GUI
block (DC) timing generator should provide the display timings. The VGA slaves its dis-
play activity to the regular Display Controller sync and displays enable signals. The VGA
can be made to center or scale its pixel output depending on a control bit in the VGA
ExtendedModeControl register (CRTC Index 43h[3]). This is a writable bit.
0: VGA uses its own timer when it is enabled.
1: The Display Controller's “default” timing generator is used to control the display of the
screen image.
Frame Dirty Mode.
0: Frame buffer writes mark associated scan line dirty. Used when DC_GFX_PITCH
1: Frame buffer writes mark entire frame as dirty. Used when DC_GFX_PITCH (DC
Static Frame Mode. If compression is enabled (CMPE, bit 5 = 1), this bit selects when to
update dirty scan lines.
0: Update any dirty scan lines every frame when compression is enabled.
1: Update any dirty scan lines every other frame when compression is enabled.
Display FIFO High Priority End Level. This field specifies the depth of the display FIFO
(in 64-bit entries x 4) at which a high-priority request previously issued to the memory
controller ends. The value is dependent upon display mode. This field should always be
non-zero and should be larger than the start level.
Display FIFO High Priority Start Level. This field specifies the depth of the display
FIFO (in 64-bit entries x 4) at which a high-priority request is sent to the memory control-
ler to fill up the FIFO. The value is dependent upon display mode. This field should
always be non-zero and should be less than the high-priority end level.
VGA Enable.
0: Normal Display Controller operation.
1: Allow the hardware VGA block use of the display FIFO and the memory request inter-
When changing the state of this bit, both Display Controller and VGA (which is part of the
Display Controller) should be stopped, and not actively fetching and displaying data.
No other Display Controller features operate with the VGA pass-through feature enabled,
with the exception of the CRC/signature feature and the timing generator (when VGA
fixed timings are enabled, bit 18 = 0). All other features should be turned off to prevent
interference with VGA operation.
skip certain video lines to support downscaling in the display filter.
(DC Memory Offset 34h[15:0]) is equal to 1 KB, 2 KB, or 4 KB.
Memory Offset 34h[15:0]) is not equal to 1 KB, 2 KB, or 4 KB.
face. The VGA hsync, vsync, blank, and pixel outputs are routed through the back
end of the Display Controller pixel and sync pipeline and then to the I/O pads.
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