AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 265

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AGXD533AAXF0CC

Manufacturer Part Number
AGXD533AAXF0CC
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of AGXD533AAXF0CC

Device Core
X86
Device Core Size
64b
Frequency (max)
400MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5V
Operating Supply Voltage (max)
1.58V
Operating Supply Voltage (min)
1.42V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
368
Package Type
BGD
Lead Free Status / Rohs Status
Not Compliant
Display Controller Register Descriptions
6.6.1.5
MSR Address
Type
Reset Value
AMD Geode™ GX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:32
31:4
31:8
Bit
Bit
7:6
32
3
2
1
0
GLD Power Management MSR (GLD_MSR_PM)
Name
UNEXP_TYPE_
ERR_FLAG
RSVD
DFIFO_ERR_EN
SMI_ERR_EN
UNEXP_ADDR_
ERR_EN
UNEXP_TYPE_
ERR_EN
Name
RSVD
RSVD
PMODE3
80002004h
R/W
00000000_00000000h
GLD_MSR_ERROR Bit Descriptions (Continued)
Description
Reserved. Write as 0.
Reserved. Write as 0.
Power Mode 3 (VGA DOTCLK). This field controls the internal clock gating for the
DOTCLK to the VGA block.
00: Disable clock gating. Clocks are always on.
01: Enable active hardware clock gating. Clock goes off whenever this module’s cir-
10: Reserved.
11: Reserved.
Description
Unexpected Type Error Flag. If high, records that an ERR has occurred because
the Display Controller received a GLIU transaction with an undefined or unexpected
type. Write 1 to clear; writing 0 has no effect.
Reserved. Write as 0.
Display FIFO Underrun Error Enable. Write 0 to enable generation of the ERR sig-
nal if the display FIFO runs dry. Error reported in bit 35.
Uncleared SMI Error Enable. Write 0 to enable generation of the ERR signal if a
second SMI occurs before the first SMI is serviced. Error reported in (bit 34).
Unexpected Address Error Enable. Write 0 to enable generation of the ERR signal
if the Display Controller receives a GLIU transaction with the exception flag set. Error
reported in (bit 33).
Unexpected Type Error Enable. Write 0 to enable generation of the ERR signal if
the Display Controller receives a GLIU transaction with an undefined or unexpected
type and set flag (bit 32).
cuits are not busy.
GLD_MSR_PM Bit Descriptions
RSVD
GLD_MSR_PM Register Map
RSVD
9
8
31505E
7
6
5
4
3
2
1
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