AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 394

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

6.10.1.3
MSR Address
Type
Reset Value
394
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:20
15:4
Bit
19
18
17
16
3
2
1
0
GLD SMI MSR (GLD_MSR_SMI)
Name
RSVD
PML2_SSMI_FLAG
PMCNT_SSMI_
FLAG
DBG_ASMI_FLAG
ERR_ASMI_FLAG
RSVD
PML2_SSMI_EN
PMCNT_SSMI_EN
DBG_ASMI_EN
ERR_ASMI_EN
4C002002h
R/W
00000000_0000000Fh
RSVD
31505E
Description
Reserved. Write as read.
Power Management GLCP_LVL2 Synchronous SMI Flag. If high, records that
an SSMI was generated due to a read of the GLCP_LVL2 register (MSR
4C000019h). Write 1 to clear; writing 0 has no effect. PML2_SSMI_EN (bit 3) must
be low to generate SSMI and set flag.
Power Management GLCP_CNT Synchronous SMI Flag. If high, records that an
SSMI was generated due to a write of the GLCP_CNT register (MSR 4C000018h).
Write 1 to clear; writing 0 has no effect. Write 1 to clear; writing 0 has no effect.
PMCNT_SSMI_EN (bit 2) must be low to generate SSMI and set flag.
Debug Asynchronous SMI Flag. If high, records that an ASMI was generated due
to a debug event or PROCSTAT access (MSR 4C00000Dh). Write 1 to clear; writ-
ing 0 has no effect. DBG_ASMI_EN (bit 1) must be low to generate ASMI and set
flag.
Error Signal Asynchronous SMI Flag. If high, records that an ASMI was gener-
ated due to the ERR signal. Write 1 to clear; writing 0 has no effect. ERR_ASMI_EN
(bit 0) must be low to generate ASMI and set flag.
Reserved. Write as read.
Power Management GLCP_LVL2 Synchronous SMI Enable. Write 0 to enable
power management logic to generate an SSMI when the GLCP_LVL2 register
(MSR 4C000019h) is read and to set flag (bit 19).
Power Management GLCP_CNT Synchronous SMI Flag. Write 0 to enable
power management logic to generate an SSMI when the GLCP_CNT register (MSR
4C000018h) is written and set flag (bit 18).
Debug Asynchronous SMI Flag. Write 0 to enable the debug logic to generate an
ASMI and set flag (bit 17).
Error Signal Asynchronous SMI Flag. Write 0 to enable any GLIU1device ERR
signal (including GLCP) to cause an ASMI and set flag (bit 16).
GLD_MSR_SMI Bit Descriptions
GLD_MSR_SMI Register Map
RSVD
GeodeLink™ Control Processor Register Descriptions
RSVD
AMD Geode™ GX Processors Data Book
9
8
7
6
5
4
3
2
1
0