PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 106

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

7.0 X-Bus Extension
Notes: This section applies to the PC87393 and PC87393F only.
7.1 OVERVIEW
The PC8739x provides an X-Bus extension to the LPC bus to enable the ISA-like interface to external 8-bit peripherals. De-
code logic, described in the Device Architecture and Configuration chapter, defines the addresses for which the X-Bus gen-
erates transactions. These transactions may be in the I/O address space and the memory address space or in the FWH
memory address space. Using the X-Bus interface, the PC8739x serves as a bridge for such transactions into the X-Bus.
Figure 21 is a schematics block diagram of the X-Bus bridging function. For details on the decoder functions, see the Device
Architecture and Configuration chapter. All other functions are described in detail in this chapter.
7.2 IRQ ROUTING
The PC8739x supports up to four IRQ inputs, PIRQA through PIRQD. These pins may be used to support legacy devices
that are connected on the X-Bus. The PC8739x enables any of these interrupts to be routed to any one of fifteen host IRQs.
The IRQ inputs are mapped by X-Bus PIRQA-D Mapping registers at F8h and F9h. XIRQCA through XIRQCD registers en-
able the user to define the interrupt as active high or low, and to route it to a wake-up event.
7.3 X-BUS TRANSACTIONS
The X-Bus extension supports 8-bit I/O or memory read/write cycles.
The zone mapping of the chip select signals determines how X-Bus read and write cycles correspond to memory and I/O
bus cycles. The zone mapping to a select signal, XCS1-0, must be enabled regardless of whether the I/O device is using
the chip select signal. Signal mapping to a pin may be disabled when the select signal is not required for an off-chip interface.
Bus
LPC
FWH-related descriptions apply to the PC87393F only.
Serializer
IRQ
Device Architecture Component
Figure 21. X-Bus Block Diagram
Configuration
Address
Memory
Decoder
Address
Decoder
X-Bus
I/O
106
IRQ Router
X-Bus Interface
Generator
Cycle
Bus
PIRQ(A-D)
XA19-0
XD7-0
XIORD XIOWR
XRD XWR
XSTB2-0
XRDY
XCS0
XCS1
XCNF2-0
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