PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 75

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

3.0 General-Purpose Input/Output (GPIO) Port
The GPEVST register is a general-purpose edge detector which may be used to reflect the event source pending status for
edge-triggered events.
The term active edge refers to a change in a GPIO pin level that matches the Event Polarity bit (1 for rising edge and 0 for
falling edge). Active level refers to the GPIO pin level that matches the Event Polarity bit (1 for high level and 0 for low level).
The corresponding bit of the GPEVST register is set by hardware whenever an active edge is detected, regardless of any
other bit settings. Writing 1 to the Status bit clears it to 0. Writing 0 is ignored.
A GPIO pin is in event pending state if the corresponding bit of the GPEVEN register is set and either:
The target means of system notification is asserted if at least one GPIO pin is in event pending state.
The selection of the target means of system notification is determined by the GPEVR register. If IRQ is selected as one of the
means for the system notification, the specific IRQ line is determined by the IRQ selection procedure of the device configura-
tion. The assertion of any means of system notification is blocked when the GPIO functional block is deactivated.
If the output of a GPIO pin is enabled, it may be put in event pending state by the software when writing to the GPDO register.
An pending edge event may be cleared by clearing the corresponding GPEVST bit. However, a level event source may not
be released by software (except for disabling the source), as long as the pin is in active level. When level event is used, it
is recommended to disable the input debouncer.
Upon de-activation of the GPIO port, the GPEVST register is cleared and access to both the GPEVST and GPEVEN regis-
ters is disabled. All system notification means including the target IRQ line are detached from the GPIO and de-asserted.
Before enabling any system notification, it is recommended to set the desired event configuration, and then verify that the
status registers are cleared.
3.4 GPIO PORT REGISTERS
The register maps in this chapter use the following abbreviations for Type:
Event Pending Indicator
The Event Type is level and the pin is in active level, or
The Event Type is edge and the corresponding bit of the GPEVST register is set.
R/W = Read/Write
R = Read from a specific address returns the value of a specific register. Write to the same address is to a different
register.
W = Write
RO = Read Only
R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
GPIO Pin Event Routing Register
Routing
Enable
SMI
Bit 1
Routing
Enable
IRQ
Bit 0
Figure 11. GPIO Event Routing Mechanism
Event
Routing
Logic
75
(Continued)
Routed Events
from other GPIO Pins
SMI
IRQ
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