PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 30

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

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2.0 Device Architecture and Configuration
F0h-FEh
Index
Index
Index
70h
71h
74h
75h
Interrupt Request
Interrupt Number
and Wake-Up on
Register Name
Register Name
Register Name
Logical Device
DMA Channel
DMA Channel
Configuration
IRQ Enable
Type Select
Select 0
Select 1
Table 12. Special Logical Device Configuration Registers
Indicates selected interrupt number.
Bits 7-5 - Reserved.
Bit 4 - Enables wake-up on the IRQ of the logical device. When enabled, IRQ
assertion triggers a wake-up event.
Bits 3–0 select the interrupt number. A value of 1 selects IRQL1. A value of 15
selects IRQL15. IRQL0 is not a valid interrupt selection and represents no interrupt
selection.
Indicates the type and level of the interrupt request number selected in the previous
register.
If a logical device supports only one type of interrupt, this register is read only.
Bits 7–2 - Reserved.
Bit 0 - Type of interrupt request selected in the previous register.
Bit 1 - Level of the interrupt request selected in the previous register.
Indicates selected DMA channel for DMA 0 of the logical device (0 - The first DMA
channel in case of using more than one DMA channel).
Bits 7-3 - Reserved.
Bits 2-0 select the DMA channel for DMA 0. The valid choices are 0-3, where a
value of 0 selects DMA channel 0, 1 selects channel 1, etc.
Indicates selected DMA channel for DMA 1 of the logical device (1 - The second
DMA channel in case of using more than one DMA channel).
Bits 7-3 - Reserved.
Bits 2-0 select the DMA channel for DMA 1. The valid choices are 0-3, where a
value of 0 selects DMA channel 0, 1 selects channel 1, etc.
Special (vendor-defined) configuration options
Table 10. Interrupt Configuration Registers
0: Disabled (default)
1: Enabled
0: Edge
1: Level
0: Low polarity
1: High polarity
A value of 4 indicates that no DMA channel is active.
The values 5-7 are reserved.
A value of 4 indicates that no DMA channel is active.
The values 5-7 are reserved.
Table 11. DMA Configuration Registers
30
(Continued)
Description
Description
Description