PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 23

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

1.0 Signal/Pin Connection and Description
1.5.11 Strap Configuration
1.5.12 Wake-Up Control
1.5.13 WATCHDOG Timer
1.5.14 X-Bus Extension (PC87393 and PC87393F)
WDO
BADDR
TEST
XCNF2-0
PWUREQ
XRD
XWR
XIORD
Signal
Signal
Signal
Signal
1.
In the PC87391 and PC87392, the XCNFi signals must be set to this value. This is value is guaranteed by
the internal pull-down resistors, as long as the pins are not connected, or the load is small enough.
5
66
5
4
83, 71
Pin/s
Pin/s
Pin/s
59
61
58
90, 4,
Pin/s
I/O Buffer Type Power Well
I/O Buffer Type Power Well
I/O Buffer Type Power Well
O
O
O
O
O
I/O Buffer Type Power Well
I
I
I
OD
OD
O
O
O
IN
IN
IN
6
, O
3/6
3/6
3/6
STRP
STRP
STRP
6
3/6
V
V
V
V
V
DD
V
V
V
DD
DD
DD
DD
DD
DD
DD
WATCHDOG Out. Low level indicates that the WATCHDOG Timer
has reached its time-out period without being retriggered.
The output type and an optional pull-up are configurable.
Power-Up Request. Active (low) level indicates that wake-up
event has occurred, and causes the chipset to turn the power
supply on, or to exit its current sleep state.
Read. Active (low) level indicates read cycle on the X-Bus
Extension.
Write. Active (low) level indicates write cycle on the X-Bus
Extension.
I/O Read. Active (low) level indicates I/O read cycle on the X-Bus
Extension. This signal is for devices that require separate
read/write inputs for memory and I/O.
Base Address. Sampled at Reset to determine the base
address of the configuration Index-Data register pair, as follows.
No pull-up resistor:
10K external pull-up resistor:
Test. Forces the device into test mode if an external pull-up
resistor is connected. Otherwise, the pin is pulled to ‘0’ (zero) by
the internal resistor.
X-Bus Reset Configuration Mode. Forces the X-Bus
transaction to be in one of the following modes: no BIOS, normal
or latch. For details, see Chapter 7.
Pins
2 1 0
x 0 0
x 0 1
0 1 0
1 1 0
0 1 1
1 1 1
Pulled to 0 by internal resistor, or set to 1 by external 10K pull-up
resistor.
23
(Continued)
No BIOS
Normal Mode, XRDY disabled
Latch Mode, XA12-19, XRDY enabled
Latch Mode, GPIO10-17, XRDY enabled
Latch Mode, XA12-19, XRDY disabled
Latch Mode, GPIO10-17, XRDY disabled
Functionality
1
Description
Description
Description
Description
2Eh-2Fh
4Eh-4Fh
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