PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 116

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

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7.0 X-Bus Extension
7.4.5
This set of four registers defines the mapping of the four PIRQ signals. Each registers is associated with one of the four
PIRQ inputs, as follows:
Location:
Location:
Location:
Location:
Type:
Bit
Name
Reset
7-4
Bit
3
2
1
0
X-Bus PIRQx Input Registers (XIRQCA to XIRQCD)
0: Disabled (default).
1: Enabled.
Reserved
PIRQ Polarity Inversion. This bit controls the polarity of the IRQ signal sent through the IRQ Serializer (see
Table 32). This bit is reset to ’0’.
PIRQ Enable. When this bit is set, it enables the interrupt. Ignored when the IRQ is mapped to zero (see
Section 2.2.3).
0: Disabled (default).
1: Enabled.
PIRQ Polarity. This bit specifies the active level of the incoming IRQ signal.
0: Active low (default).
1: Active high.
Power-Up Request Enable. An IRQ event is routed to the PWUREQ output.
Offset 04h (XIRQCA)
Offset 05h (XIRQCB)
Offset 06h (XIRQCC)
Offset 07h (XIRQCD)
R/W
7
0
(Continued)
PIRQ Polarity
6
0
Inversion
Reserved
0
0
1
1
Table 32. IRQ Polarity Control
5
0
PIRQ Polarity
0
1
0
1
116
Description
4
0
Serial IRQ Polarity
Inversion
Polarity
PIRQ
3
0
PIRQx
PIRQx
PIRQx
PIRQx
Enable
PIRQ
2
0
Polarity
PIRQ
1
0
PWUREQ
Enable
0
0