PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 79

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

3.0 General-Purpose Input/Output (GPIO) Port
3.4.6
Location:
Type:
3.4.7
Location:
Type:
Bit
Name
Reset
Bit
Name
Reset
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
GPIO Event Enable Register (GPEVEN)
GPIO Event Status Register (GPEVST)
Event Enable. Bits 7-0 correspond to pins 7-0 respectively. Each bit enables system notification triggering by
the corresponding GPIO pin. The bit has no effect on the corresponding Status bit in the GPEVST register.
0: IRQ generation by corresponding GPIO pin masked
1: IRQ generation by corresponding GPIO pin enabled
Status. Bits 7-0 correspond to pins 7-0 respectively. Each bit is an edge detector that is set to 1 by the hardware
upon detection of an active edge (i.e. edge that matches the IRQ Polarity bit) on the corresponding GPIO pin.
This edge detection is independent of the Event Type or the Event Enable bit in the GPEVEN register. However,
the bit may reflect the event status for enabled, edge-trigger event sources. Writing 1 to the Status bit clears it
to 0.
0: No active edge detected since last cleared
1: Active edge detected
Device specific
R/W
Device specific
R/W1C
7
0
7
0
6
0
6
0
5
0
5
0
Description
Description
79
4
0
4
0
Event Enable
Status
(Continued)
3
0
3
0
2
0
2
0
1
0
1
0
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0
0
0
0