PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 9

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

Table of Contents
7.0
8.0
6.4
X-Bus Extension
7.1
7.2
7.3
7.4
7.5
7.6
Legacy Functional Blocks
8.1
8.2
8.3
8.4
6.3.5
6.3.6
MIDI PORT BITMAP ................................................................................................................ 105
OVERVIEW ............................................................................................................................. 106
IRQ ROUTING ......................................................................................................................... 106
X-BUS TRANSACTIONS ......................................................................................................... 106
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
X-BUS CONFIGURATION REGISTERS ................................................................................. 112
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10
X-BUS EXTENSION BITMAP .................................................................................................. 120
FLOPPY DISK CONTROLLER (FDC) ..................................................................................... 121
8.1.1
8.1.2
8.1.3
PARALLEL PORT .................................................................................................................... 123
8.2.1
8.2.2
8.2.3
UART FUNCTIONALITY (SP1 AND SP2) ............................................................................... 126
8.3.1
8.3.2
8.3.3
8.3.4
IR FUNCTIONALITY (SP2) ..................................................................................................... 131
8.4.1
USAGE HINTS ....................................................................................................................... 118
MIDI Command Register (MCOM) ............................................................................ 103
MIDI Control Register (MCNTL) ................................................................................ 104
Programmable I/O Range Chip Select ...................................................................... 107
LPC and FWH Address to X-Bus Address Translation ............................................. 107
Extended Read/Write Signal Mode ........................................................................... 108
Indirect Memory Read and Write Transaction ........................................................... 108
Normal Address Mode X-Bus Transactions .............................................................. 108
Latched Address Mode X-Bus Transactions ............................................................. 110
X-Bus Register Map .................................................................................................. 112
X-Bus Configuration Register (XBCNF) .................................................................... 112
X-Bus Select 0 Configuration Register (XZCNF0) ..................................................... 114
X-Bus Select 1 Configuration Register (XZCNF1) ..................................................... 115
X-Bus PIRQx Input Registers (XIRQCA to XIRQCD) ................................................ 116
X-Bus Indirect Memory Address Register 0 (XIMA0) ................................................ 117
X-Bus Indirect Memory Address Register 1 (XIMA1) ................................................ 117
X-Bus Indirect Memory Address Register 2 (XIMA2) ................................................ 118
X-Bus Indirect Memory Address Register 3 (XIMA3) ................................................ 118
X-Bus Indirect Memory Data Register (XIMD) ........................................................... 118
General Description ................................................................................................... 121
FDC Register Map ..................................................................................................... 121
FDC Bitmap Summary ............................................................................................... 122
General Description ................................................................................................... 123
Parallel Port Register Map ......................................................................................... 123
Parallel Port Bitmap Summary .................................................................................. 124
General Description ................................................................................................... 126
UART Mode Register Bank Overview ....................................................................... 126
SP1 and SP2 Register Maps for UART Functionality ................................................ 127
SP1 and SP2 Bitmap Summary for UART Functionality ........................................... 129
General Description ................................................................................................... 131
(Continued)
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