PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 63

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

2.0 Device Architecture and Configuration
(Continued)
Usage Hints: To operate GMP enhanced features, make sure to locate its base address within the LPC Wide Generic ad-
dress range.
When bit 3 of the GMP configuration register is set to 0 (default), the GMP operates in Legacy mode. In this mode, only the
Game Port Legacy Status (GMPLST) register of the GMP is accessible, and is mapped to the base address of the GMP.
For example, if GMP configuration bit 3 is set to 0 and the base address is programmed to 203h, the GMPLST register is
mapped to address 203h, and is the only user-accessible GMP register.
The GMP is also forced to operate in Legacy mode if the programmed base address is not 16-byte aligned; i.e. bits 3-0 of
the base address are not all 0’s.
When bit 3 of the GMP register is set to 1 and the programmed GMP base address is 16-byte aligned; i.e., bits 3-0 of the
base address are all 0’s, the GMP can be operated in Enhanced mode. In this condtion, all the registers listed in the GMP
chapter are accessible.
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