PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 76

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

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3.0 General-Purpose Input/Output (GPIO) Port
3.4.1
This is a group of eight identical configuration registers, each of which is associated with one GPIO pin. The entire set is
mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register that functions as an index
register, and the specific GPCFG register that reflects the configuration of the currently selected pin. For details on the
GPSEL register, refer to the Device Architecture and Configuration chapter.
Bits 4-6 are applicable only for the enhanced GPIO port with event detection support. In the basic port, these bits are re-
served, return 0 on read and have no effect on port functionality.
Location:
Type:
Bit
Name
Reset
Bit
7
6
5
4
3
2
1
0
GPIO Pin Configuration (GPCFG) Register
Reserved
Event Debounce Enable
0: Disabled
1: Enabled (default)
Event Polarity. This bit defines the polarity of the signal that causes a detection of an event from the
corresponding GPIO pin (falling/low or rising/high).
0: Falling edge or low level input (default)
1: Rising edge or high level input
Event Type. This bit defines the signal type that causes detection of an event from the corresponding GPIO pin.
0: Edge input (default)
1: Level input
Lock. This bit locks the corresponding GPIO pin. Once this bit is set to 1 by software, it can only be cleared to
0 by system reset or power-off. Pin multiplexing is functional until the Multiplexing Lock bit is 1. (Refer to the
Device Architecture and Configuration chapter.)
0: No effect (default)
1: Direction, output type, pull-up and output value locked
Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin.
It supports open-drain output signals with internal pull-ups and TTL input signals
0: Disabled
1: Enabled (default)
Output Type. This bit controls the output buffer type (open-drain or push-pull) of the corresponding GPIO pin.
0: Open-drain (default)
1: Push-pull
Output Enable. This bit indicates the GPIO pin output state. It has no effect on input.
0: TRI-STATE (default)
1: Output enabled
Device specific
R/W (bit 3 is set only)
Reserved
7
0
Debounce
Enable
Event
6
1
Polarity
Event
5
0
Event Type
Description
76
4
0
(Continued)
Lock
3
0
Pull-Up
Control
2
1
Output
Type
1
0
Output
Enable
0
0