PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 61

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

2.0 Device Architecture and Configuration
2.16 WATCHDOG TIMER (WDT) CONFIGURATION
2.16.1 Logical Device 10 (WDT) Configuration
Table 25 lists the configuration registers which affect the WATCHDOG Timer. Only the last register (F0h) is described here.
See Sections 2.2.3 and 2.2.4 for a detailed description of the others.
2.16.2 WATCHDOG Timer Configuration Register
This register is reset by hardware to 02h.
Location:
Type:
Bit
Name
Reset
7-4
Bit
3
2
1
0
Index
Reserved
Output Type. This bit controls the buffer type (open-drain or push-pull) of the WDO pin.
0: Open-drain (default)
1: Push-pull
Internal Pull-Up Enable. This bit controls the internal pull-up resistor on the WDO pin.
0: Disabled (default)
1: Enabled
Power Mode Control
0: Low power mode:
30h
60h
61h
70h
71h
74h
75h
F0h
1: Normal power mode:
TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.
0: Disabled (default)
1: Enabled
WATCHDOG Timer clock disabled. WDO output signal is set to 1. Registers are accessible and maintained
(unlike Active bit in Index 30h that also prevents access to WATCHDOG Timer registers).
WATCHDOG Timer clock enabled. WATCHDOG Timer is functional when the logical device is active (default).
Index F0h
R/W
Activate. When bit 0 is cleared, the registers of this logical device are not
accessible.
Base Address MSB register
Base Address LSB register. Bits 1 and 0 (for A1 and A0) are read only, 00b. R/W
Interrupt Number (for routing the WDO signal) and Wake-Up on IRQ Enable
register.
Interrupt Type. Bit 1 is read/write. Other bits are read only.
Report no DMA assignment
Report no DMA assignment
WATCHDOG Timer Configuration register
7
0
6
0
Reserved
Configuration Register or Action
Table 25. WDT Configuration Registers
5
0
Description
61
4
0
(Continued)
Output
Type
3
0
Internal
Pull-Up
Enable
2
0
Type
R/W
R/W
R/W
R/W
R/W
RO
RO
Control
Power
Mode
1
1
Reset
00h
00h
00h
00h
03h
04h
04h
02h
TRI-STATE
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Control
0
0