PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 80

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

4.0 WATCHDOG Timer (WDT)
4.1 OVERVIEW
The WATCHDOG Timer prompts the system via SMI or interrupt when no system activity is detected on a predefined selec-
tion of system events for a predefined period of time (1 to 255 minutes).
The WATCHDOG Timer monitors two maskable system events: the interrupt request lines of the two serial ports (UART1
and UART2). The system prompt is performed by asserting a special-purpose output pin (WDO), which can be attached to
external SMI. Alternatively, this indication can be routed to any arbitrary IRQ line and is also available on a status bit that
can be read by the host.
This chapter describes the generic WATCHDOG Timer functional block. A device may include a different implementation.
For device specific implementation, see the Device Architecture and Configuration chapter.
4.2 FUNCTIONAL DESCRIPTION
The WATCHDOG Timer consists of an 8-bit counter and three registers: Timeout register (WDTO), Mask register (WDMSK)
and Status register (WDST). The counter is an 8-bit down counter that is clocked every minute and is used for the timeout
period countdown. The WDTO register holds the programmable timeout, which is the period of inactivity after which the
WATCHDOG Timer prompts the system (1 to 255 minutes). The WDMSK register determines which system events are en-
abled as WATCHDOG Timer trigger events to restart the countdown. The WDST register holds the WATCHDOG Timer sta-
tus bit that reflects the value of the WDO pin and indicates that the timeout period has expired.
Figure 12 shows the functionality of the WATCHDOG Timer.
Upon reset, the Timeout register (WDTO) is initialized to zero, the timer is deactivated, the WDO is inactive (high) and all
trigger events are masked.
Upon writing to the WDTO register, the timer is activated while the counter is loaded with the timeout value and starts count-
ing down every minute. If a trigger event (unmasked system event) occurs before the counter has expired (reached zero),
the counter is reloaded with the timeout period (from WDTO register) and restarts the countdown. If no trigger event occurs
before the timeout period expires, the counter reaches zero and stops counting. Consequently, the WDO pin is asserted
(pulled low) and the WDO Status bit is cleared to 0.~
Writing to the WDTO register de-asserts the WDO output (released high) and sets the WDO Status bit to 1. If a non-zero
value is written, a new countdown starts as described above. If 00h is written, the timer is deactivated.
To summarize, the WDO output is de-asserted (high) and the Status bit is set to 1 (inactive) upon:
The WDO output is asserted (low) and the WDO status is set to zero (active) when the counter reaches zero.
When an IRQ is assigned to the WATCHDOG Timer (through the WATCHDOG Timer device configuration), the selected
IRQ level is active as long as the WDO status bit is low (active).
Reset
Activating the WATCHDOG Timer or
Writing to the WDTO register.
WDMSK
Serial Port 2 IRQ
Serial Port 1 IRQ
Reserved
Reserved
Register
Enable Bits
3
2
1
Figure 12. WATCHDOG Timer Functional Diagram
0
Write
Reload
80
Load
WDTO Register
Zero Detector
Data Bus
Status Bit
Timer
1 Minute
Clock
Interrupt
WDO
www.national.com