PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 77

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

3.0 General-Purpose Input/Output (GPIO) Port
3.4.2
This is a group of eight identical configuration registers, each of which is associated with one GPIO pin. The entire set is
mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register that functions as an index
register, and the specific GPER register that reflects the routing configuration of the currently selected pin. For details on the
GPSEL register, refer to the Device Architecture and Configuration chapter.
This set of registers is applicable only for the enhanced GPIO port with event detection support. In the basic port this register
set is reserved, returns 0 on read and has no effect on port functionality.
Location:
Type:
3.4.3
Bit
Name
Reset
7-2
Bit
1
0
GPIO Pin Event Routing (GPEVR) Register
GPIO Port Runtime Register Map
event to SMI.
0: Disabled (default)
1: Enabled
GPIO Event to IRQ Enable. This bit is used to enable/disable the routing of the corresponding detected GPIO
event to IRQ.
0: Disabled
1: Enabled (default)
Reserved
GPIO Event to SMI Enable . This bit is used to enable/disable the routing of the corresponding detected GPIO
Device specific
R/W
Device specific
Device specific
Device specific
Device specific
1. The location of this register is defined in the Device Architecture and Configuration chap-
ter in Section 2.15.1.
7
0
Offset
1
1
1
1
6
0
Mnemonic
GPEVEN
GPEVST
GPDO
GPDI
5
0
Reserved
GPIO Event Enable
GPIO Event Status
Register Name
GPIO Data Out
GPIO Data In
Description
77
4
0
(Continued)
3
0
R/W1C
Type
R/W
R/W
RO
2
0
GPIO Event
Enable
to SMI
Section
3.4.4
3.4.5
3.4.6
3.4.7
1
0
GPIO Event
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Enable
to IRQ
0
1