AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 108

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.2.14.9
9.2.14.10
32002F–03/2010
Debug Instruction Register (DINST)
Peripheral Debug Register (PDBG)
Table 9-12.
The Debug Instruction Register contains the instruction to be executed in OCD Mode. The CPU
fetches and executes the instruction faster than they can be written by the Debug port. DINST is
also used to store the instruction to replace the breakpoint instruction.
Table 9-13.
The Peripheral Debug Register controls the operation of modules in debug mode. If the DC.RID
bit is set, the CPU is in debug mode and the PDBG bit for a module is set this module is kept
running in debug mode. Otherwise the module is stopped. The mapping between the bits in this
register and modules are part specific and are described in the OCD module configuration sec-
tion of the part datasheet.
Table 9-14.
R/W
R
R
R
R
R
R/W
R/W
R/W
R/W
Bit Number
4
3
2
1
0
Bit Number
31:0
Bit Number
31:0
Development Status register
Debug Instruction register
Debug Instruction register
Field Name
STP
Reserved
HWB
SWB
SSS
Field Name
DINST
Field Name
PDBG
Init. Val.
0
0
0
0
0
Init. Val.
0
Init. Val.
0
Description
STP - Stop Status
STP is set if OCD Mode is entered from sleep
mode. This bit can be used by the debugger to
determine the proper return sequence from OCD
Mode. This bit is cleared when OCD Mode is
exited.
HWB - Hardware Breakpoint Status
This bit is set if Debug Mode was entered due to a
hardware breakpoint. The BP[7:0] bits should be
examined to determine the breakpoint(s) which
triggered. This bit is cleared when Debug Mode is
exited.
SWB - Software Breakpoint Status
This bit is set if Debug Mode was entered due to a
breakpoint instruction being executed. Returning
from a software breakpoint may require special
handling by the debugger. This bit is cleared when
Debug Mode is exited.
SSS - Single Step Status
This bit is set when Debug Mode is entered due to
a single step. This bit is cleared when Debug
Mode is exited.
Description
DINST - Debug Instruction
The instruction to be executed on the CPU.
Description
PDBG - Peripheral debug.
0 = The peripheral is running in debug mode.
1 = The peripheral is stopped in debug mode.
AVR32
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