AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 98

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.2.8
9.2.9
9.2.10
9.2.11
32002F–03/2010
OCD Register Access
OCD features in Debug Mode
OCD Registers Accessed by CPU
Runtime write access to OCD registers
Decrement RAR_DBG in Debug Mode to return to the sleep instruction. This places the CPU
back into sleep mode after exiting Debug Mode.
The OCD registers control the OCD system. Their specification is based on the Nexus Recom-
mended Registers as outlined in the Nexus Standard Specification [IEEE-ISTO 5001™-2003].
All registers can be accessed through the JTAG interface.
When the CPU executes in Debug Mode, certain OCD features will be disabled. The following
table indicates how the various OCD features will behave in Debug Mode. For more information
on the specific features, please see the indicated page.
Table 9-2.
A monitor program running on the target can access the OCD registers through mtdr and mfdr
instructions. These instructions transfer data between a register in the register file and an OCD
register, according to the register index given in
instructions can also be used in OCD mode to transfer information from the register file and sys-
tem registers to the debugger, through the Debug Communication Mechanism.
The OCD registers can always be accessed by JTAG when the when the OCD system is not
enabled or the CPU is in OCD Mode. The OCD registers can also be read by JTAG at any time,
and by the CPU in any privileged mode.
When the CPU is in other modes - either running normal code, or executing in Monitor Mode -
the OCD registers can be written by JTAG as specified in Table 9-3. If the registers are
accessed in another way than specified, undefined operation may result.
The OCD Register Protect (ORP) bit in DC define the allowed write access to OCD registers in
privileged modes. If the ORP bit in DC does not allow CPU access to OCD registers in the cur-
Feature
Program Breakpoints (HW)
Software Breakpoints
Data Breakpoints
Watchpoints (program and data)
Program Trace
Data Trace
Ownership Trace
Debug Communication Mechanism
OCD features in Debug Mode
Available in Debug Mode?
Yes, in Monitor Mode when SR:DM is cleared
Yes, in Monitor Mode when SR:DM is cleared
Yes, in Monitor Mode when SR:DM is cleared
Yes, in Monitor Mode
No
No
Yes
Yes
“OCD Register Summary” on page
AVR32
153. These
98