AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 77

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8.8
8.9
8.10
32002F–03/2010
Divide instructions
Saturate instructions
Load and store instructions
These instructions require several cycles in the EX stage to complete. The divs and divu instruc-
tions will be aborted immediately if any interrupts are pending, in order to limit the interrupt
latency. The divide instructions are faster in revision 2 than in revision 1 of the AVR32UC CPU.
Table 8-5.
1.) 35 cycles in revision 1 of the CPU
These instructions perform arithmetic operations with possible saturation.
Table 8-6.
This group includes all the load and store instructions. The address calculations are performed
by the adder in the EX stage. The EX adder also performs the writeback address calculation for
the autoincrement and autodecrement operation.
Loaded data are available at the end of the cycle in the EX stage. Byte and halfword data must
be extended and rotated before they are valid. This is performed in the EX stage. Ldins and
ldswp instructions also require modification in the EX stage before their results are valid. Stswp
instructions require modification before their data is output to the memory interface. This modifi-
cation is performed in the EX stage.
Mnemonics
divs
divu
Mnemonics
satadd.h
satadd.w
satsub.h
satsub.w
satrnds
satrndu
sats
satu
Divide instructions
Saturate instructions
E
E
E
E
E
E
E
E
E
E
E
Operands
Rd, Rx, Ry
Rd, Rx, Ry
Operands
Rd, Rx, Ry
Rd, Rx, Ry
Rd, Rx, Ry
Rd, Rx, Ry
Rd, Rs, imm
Rd >> sa, b5
Rd >> sa, b5
Rd >> sa, b5
Rd >> sa, b5
Description
Divide signed.
(32 ← 32/32)
(32 ← 32%32)
Divide unsigned.
(32 ← 32/32)
(32 ← 32%32)
Description
Saturated add halfwords.
Saturated add.
Saturated subtract halfwords.
Saturated subtract.
Signed saturate from bit given by sa after a
right shift with rounding of b5 bit positions.
Unsigned saturate from bit given by sa after a
right shift with rounding of b5 bit positions.
Shift sa positions and do signed saturate from
bit given by b5.
Shift sa positions and do unsigned saturate
from bit given by b5.
AVR32
Issue
latency
1
1
1
1
1
2
2
1
1
Issue
latency
19
19
1
1
77